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CESCA Publications: 2010 and before

 

    Go to CESCA Publications: 2011 to present page.

This materials are presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders.

Publications are listed by year in reverse chronological order, and by the first author's name in alphabetical order.  Click the underlined title to view the abstract or document.  Type the author's last name or keyword in the Search box to view the relevant publications.

Year
Publication
Keywords
2010 A. Maiti, J. Casarona, L. McHale, P. Schaumont "A Large Scale Characterization of RO-PUF," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2010), Anaheim, June 2010. Authentication, Circuits, Data analysis, Delay, Field programmable gate arrays, Frequency, Hamming distance, Large-scale systems, Ring oscillators, Semiconductor device measurement
2010 A. Sinha, Z. Chen, P. Schaumont, "A Comprehensive Analysis of Performance and Side-Channel Leakage of AES SBOX Implementations in Embedded Software," Fifth Workshop on Embedded Systems Security (WESS'2010), Scottsdale, AZ, October 2010.  
2010 Ahuja, S.; Wei Zhang; Lakshminarayana, A.; Shukla, S.K.;, "A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms," VLSI Design, 2010. VLSID '10. 23rd International Conference on, Bangalore, India, pp.282-287, 3-7 Jan. 2010. C2R, Clock-gating, Hardware Coprocessor, High Level Synthesis, Power Reduction, Software Algorithms
2010 Ahuja, S.; Wei Zhang; Shukla, S.K.;, "System level simulation guided approach to improve the efficacy of clock-gating," High Level Design Validation and Test Workshop (HLDVT), 2010 IEEE International, Anaheim, CA, pp.9-16, 10-12 June 2010. Clocks, Debugging, Embedded system, Frequency, Hardware, Intellectual property, Manufacturing, Observability, Protocols, System-on-a-chip
2010 Anupam Srivastava, Huy Lam, Michael S. Hsiao, David Samuels, Carla Finkielstein, "Identification of illegal states in a discrete transition model of apoptosis signaling," in International Workshop on Bio-Design Automation (IWBDA), pp. 84-85, June 2010.  
2010 B. Bahrak, A. Deshpande, M. Whitaker, and J. Park, "BRESAP: A policy reasoner for processing spectrum access policies represented by binary decision diagrams," IEEE International Dynamic Spectrum Access Networks Symposium (DySPAN), Apr. 2010. Binary decision diagrams, Boolean functions, Cognitive radio, Communications Society, Data structures, Engines, Performance evaluation, Radio spectrum management, Regulators, USA Councils
2010 Bijoy A. Jose and Sandeep K. Shukla, "MRICDF: A Polychronous Model for Embedded Software Synthesis," Book Chapter in "Synthesis of embedded software - frameworks and methodologies for correctness by construction software design", ISBN: 978-1-4419-6399-4, Springer, MA, 2010. Circuits and systems, Computer-aided engineering (CAD, CAE) and design
2010 Bin Xue, Sandeep K. Shukla, "Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus", Journal of Electronic Testing, Vol. 26, No. 2. (1 April 2010), pp. 227-242. Latency insensitive, Periodic clock calculus, Fractional synchronizer, Scheduling, static estimation
2010 Bin Xue; Shukla, S.K.; Ravi, S.S.;, "Minimizing back pressure for latency insensitive system synthesis," 2010 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE), Grenoble, France, pp.189-198, 26-28 July 2010. back pressure, latency insensitive, strongly connected component graph, throughput
2010 Bin Xue; Shukla, S.K.;, "Optimization of back pressure and throughput for latency insensitive systems," Computer Design (ICCD), 2010 IEEE International Conference on, Amsterdam, Netherlands, pp.45-51, 3-6 Oct. 2010. Complexity theory, Gold, IP networks, Optimization, Protocols, Throughput, Upper bound
2010 Brandt, J.; Schneider, K.; Ahuja, S.; Shukla, S.K.;, "The Model Checking View to Clock Gating and Operand Isolation," Application of Concurrency to System Design (ACSD), 2010 10th International Conference on, Braga, Portugal, pp.181-190, 21-25 June 2010. clock gating, operand isolation, model checking
2010 C. Wang, R. Limaye, M. Ganai, and A. Gupta. "Trace-based symbolic analysis for atomicity violations," International Conference on Tools and Algorithms for Construction and Analysis of Systems (TACAS'10), pages 328-342. Springer 2010. LNCS 6015. Software engineering Logics and meanings of programs, Computer communication networks, Programming language, compilers interpreters, Artificial intelligence, Programming techniques
2010 Chuan Han, Yaling Yang, and Yongxiang Peng, "Optimal Cache-Based Route Repair for Real-Time Traffic", 18th IEEE International Conference on Network Protocols (ICNP), 2010. Ad hoc networks, Adaptation model, Maintenance engineering, Mobile computing, Real time systems, Routing, Routing protocols
2010 Chuan Han and Yaling Yang, "The Information Propagation Speed Upper Bound in Cognitive Radio Networks", IEEE Globecom 2010.  
2010 D. Zhou, D.S. Ha, and D.J. Inman, “Ultra Low-Power Active Wireless Sensor for Structural Health Monitoring," International Journal of Smart Structures and Systems, Vol. 6, No. 5-6, pp. 675-687, July/August, 2010. structural health monitoring; SHM; wireless sensor node; impedance-based method; temperature compensation
2010 D. Zhou, N. Kong, D.S. Ha, and D.J. Inman, “A Self-powered Wireless Sensor Node for Structural Health Monitoring,” SPIE International Symposium on Smart Structures and Materials & Nondestructive Evaluation and Health Monitoring, Vol. 7650, 765010-1 (12 pages), March 2010. Computing systems; Equipment and services; Ferroelectric materials; Sensors; Structural health monitoring
2010 G. Singh, and S.K. Shukla, "Low-Power Hardware Synthesis from Concurrent Action Oriented Specifications", Monograph, Springer, Boston, MA, 2010. Pages. 200. Hardbound.  ISBN: 1441964800 CAOS, Circuit Design, Concurrent Action-Oriented Specifications, Embedded Systems, Formal Verification, High-level Synthesis, Low-power Design
2010 Garlapati, S.; Hua Lin; Sambamoorthy, S.; Shukla, S.K.; Thorp, J.;, "Agent Based Supervision of Zone 3 Relays to Prevent Hidden Failure Based Tripping," First IEEE International Conference on Smart Grid Communications (SmartGridComm), Rockville, MD, pp.256-261, 4-6 Oct. 2010. Delay, Network topology, Power system dynamics, Power system faults, Power system protection, Relays
2010 Garlapati, S.; Shukla, S.K.; Thorp, J.;, "An algorithm for inferring master agent rules in an agent based robust Zone 3 relay architecture," North American Power Symposium (NAPS), College Station, TX, pp.1-5, 26-28 Sept. 2010. DFS, agents, cascading events, graph, hidden failure
2010 H. Zhai, S. Sha, V.K. Shenoy, S. Jung, M. Lu, K. Min, S. Lee, and D.S. Ha, “An Electronic Circuit System for Time-Reversal of Ultra-Wideband Short Impulses based on Frequency Domain Approach,” IEEE Transactions on Microwave Theory and Techniques, Vol. 58, No. 1, pp.74-86, January 2010. Electronic circuit system, frequency-domain approach, short impulses, time reversal, ultra-wideband (UWB)
2010 I. Kim, A. Maiti, L. Nazhandali, P. Schaumont, V. Vivekraja, H. Zhang, "From Statistics to Circuits: Foundations for Future Physical Unclonable Functions," chapter in "Towards Hardware Intrinsic Security," eds. A. Sadeghi, Springer Information Security and Cryptography Series, Part 1, 55-78, 2010, Springer. Data structures, Cryptology and information theory, Computer hardware, electrical engineering
2010 J. Fan, X. Guo, E. De Mulder, P. Schaumont, B. Preneel, and I. Verbauwhede, "State-of-the-art of secure ECC implementations: a survey on known side-channel attacks and countermeasures," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2010), Anaheim, June 2010. Elliptic curve, Cryptosystems, Side-channel attacks
2010 J.Y. Oh, J.K. Kim, H.-S. Lee. S.-S. Choi, and D.S. Ha, "Phase Rotation Shift Keying for Low Power and High Performance WBAN In-body systems," IEEE International Conference on Information and Communication Technology Convergence (ICTC), pp. 28-32, November, 2010. PRSK, PSSK, QPSK, WBAN, component
2010 Jens Brandt, Sandeep K. Shukla and Klaus Schneider, "Translating Concurrent Action Oriented Specifications to Synchronous Guarded Actions", In proc. of ACM Conference on Languages, Compilers and Tools for Embedded Systems(LCTES'10), 2010, Stockholm, Sweden, pp. 47-56.  
2010 Jose, B.A.; Pribble, J.; Shukla, S.K.;, "Faster Software Synthesis Using Actor Elimination Techniques for Polychronous Formalism," 10th International Conference on Application of Concurrency to System Design (ACSD), Braga, Portugal, pp.147-156, 21-25 June, 2010. embedded software, multi-clock, multirate, polychrony, prime implicate, software synthesis, synchronous programming
2010 Jose, B.A.; Shukla, S.K.;, "An alternative polychronous model and synthesis methodology for model-driven embedded software," 15th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, pp.13-18, 18-21 Jan. 2010. Computational modeling, Computer networks, Data flow computing, Embedded software, Network synthesis, Sampling methods, Signal analysis, Signal synthesis, Specification languages, Synchronization
2010 K. Kobayashi, J. Ikegami, M. Knezevid, X. Guo, S. Matuo, S. Huang, L. Nazhandali, U. Kocabas, J. Fan, A. Satoh, I. Verbauwhede, K. Sakiyama, K. Ota, "A Prototyping Platform for Performance Evaluation of SHA-3 Candidates", IEEE International Symposium on Hardware-Oriented Security and Trust (HOST2010), June 2010, pgs. 60-63. SHA-3, hardware evaluation, hardware implementation, hash function
2010 Lakshminarayana, A.; Ahuja, S.; Shukla, S.;, "Coprocessor design space exploration using high level synthesis," Quality Electronic Design (ISQED), 2010 11th International Symposium on, Santa Clara, CA, pp.879-884, 22-24 March 2010. Coprocessors, Cryptography, Field programmable gate arrays, Filters, Hardware, High level synthesis, Military computing, Performance analysis, Programming, Space exploration
2010 M. Ganai and C. Wang. "Interval analysis for concurrent trace programs using transaction sequence graphs," International Conference on Runtime Verification (RV'10), pages 253-269. Springer, 2010. Lecture Notes in Computer Science 6418. Software engineering, Algorithm analysis and problem complexity, Logic and meanings of programs, Programming techniques, Programming language, compilers, interpreters, Mathematical logic and formal languages
2010 M. Ganai, C. Wang and W. Li. "Efficient state space exploration: interleaving stateless and state-based model checking," 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD'10), pages 786-793. San Jose, CA. Bismuth, Cognition, Computational modeling, Embedded software, Heuristic algorithms, Space exploration, Switches
2010 M. Gora, A. Maiti, P. Schaumont, "A Flexible Design Flow for Software IP Binding in FPGA," IEEE Transactions on Industrial Informatics, November 2010. Design flow, field programmable gate arrays (FPGA), firmware, intellectual property, physical unclonable function, secure embedded systems, security, software binding
2010 M.B. Henry, L. Nazhandali, "From Transistors to MEMS: Throughput Aware Power-Gating in CMOS Circuits," 2010 Design, Automation & Test in Europe (DATE) Conference, Dresden, Germany, 8-12 March 2010, pgs. 130-135. Circuits, Energy consumption, Implants, Micromechanical devices, Microswitches, Radio frequency, Switches, Threshold voltage, Throughput, Wireless sensor networks
2010 Maheshwar Chandrasekar, Nikhil Rahagude, and Michael S. Hsiao "Search state compatibility based incremental learning framework and output deviation based X-filling for diagnostic test generation," in Journal of Electronic Testing: Theory and Applications, vol. 26, no. 2, pp. 165-176, April 2010. Silicon diagnosis, Diagnostic test generation, Search space pruning, X-filing
2010 Mainak Banga and Michael S. Hsiao, "Trusted RTL: Trojan detection methodology in pre-silicon designs," in Proceedings of the IEEE Hardware-Oriented Security and Trust (HOST) Symposium, June 2010, pp. 56-59. Automatic test pattern generation, Circuit faults, Circuit synthesis, Circuit testing, Costs, Design methodology, Filters, Globalization, Intellectual property, Signal processing
2010 Min Li and Michael S. Hsiao, "FSimGP2: an efficient fault simulator with GPGPU," in Proceedings of the IEEE Asian Test Symposium, December 2010, pp. 15-20. Fault simulation, compute unified device architecture (CUDA), general purpose computation on graphics processing unit (GPGPU), parallel algorithm, single instruction multiple threads (SIMT)
2010 N. J. Short, P. Lanier, K. B. Kochersberger, and A. L. Abbott, "Modal-based Camera Correction for Large Baseline Stereo Imaging", Proceedings: ASPRS 2010 Annual Conference, San Diego, CA, Apr. 2010, pp. 26-30.  
2010 N. Kong, D.S. Ha, A. Erturk, and D.J. Inman, “Resistive Impedance Matching Circuit for Piezoelectric Energy Harvesting,” Journal of Intelligent Material Systems and Structures, Vol. 21, No. 13, pp. 1293-1302, September, 2010. piezoelectric energy harvesting, resistive impedance matching, DC-DC converter
2010 N. Kong, T. Cochran, D.S. Ha, H.-C. Lin, D.J. Inman, "A Self-powered Power Management Circuit for Energy Harvested by a Piezoelectric Cantilever," Applied Power Electronics Conference and Exposition (APEC), pp. 2154 -2160, February 2010. Energy harvesting, Piezoelectric cantilever, Power management circuit
2010 N. Sinha and C. Wang. "Staged concurrent program analysis," ACM International Symposium on Foundations of Software Engineering (FSE'10), pages 47-56. Santa Fe, NM. November 2010. ACM SIGSOFT Distinguished Paper Award  
2010 N. P. Kozievitch, R. S. Torres, S. H. Park, E. A. Fox, N. Short, A. L. Abbott, S. Misra, and M. S. Hsiao, "Rethinking fingerprint evidence through integration of very large digital libraries," in Proceedings of the Workshop on Very Large Digital Libraries, September 2010.  
2010 Nanjundappa, M.; Patel, H.D.; Jose, B.A.; Shukla, S.K.;, "SCGPSim: A fast SystemC simulator on GPUs," 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, pp.149-154, 18-21 Jan. 2010. Best Paper Award at the conference Computational modeling, Concurrent computing, Discrete event simulation, Finite impulse response filter, Graphics, Parallel architectures, Parallel processing, Parallel programming, Scheduling, Yarn
2010 Neha Goel, Michael S. Hsiao, Naren Ramakrishnan, and Mohammed J. Zaki, "Mining complex Boolean expressions for sequential equivalence checking," in Proceedings of the IEEE Asian Test Symposium, December 2010, pp. 442-447. BLOSOM, Induction based proof, Re-descriptions, Sequential Equivalence Checking
2010 Nikhil Rahagude, Maheshwar Chandrasekar, and Michael S. Hsiao, "DFT + DFD: an integrated method for design for testability and diagnosability," in Proceedings of the IEEE Asian Test Symposium (ATS), December 2010, pp. 218-223. Diagnostic Resolution, Test Points, Weighted Average
2010 P. Lanier, N. J. Short, K. B. Kochersberger, and A. L. Abbott, "Modal-Based Camera Correction for Large Pitch Stereo Imaging," Proceedings: International Modal Analysis Conference (IMAC XXVIII), Jacksonville, FL, Feb. 2010.  
2010 P. Schaumont, "A Practical Introduction to Hardware/Software Codesign," 2010, Springer Circuits and Systems Series, ISBN 978-1-4419-5999-7, July 2010. Circuits and systems, Computer-aided engineering (CAD, CAE) and design, software engineering/programming and operating systems
2010 S. Deyerle, D.S. Ha, and D.J. Inman, “A Low-Power System Design for Lamb Wave Methods,” SPIE International Symposium on Smart Structures and Materials & Nondestructive Evaluation and Health Monitoring, Vol. 7650, 765019-1 (8 pages), March 2010.  
2010 S. K Shukla and J.P. Talpin, "Synthesis of Embedded software: Frameworks and Methodologies for Correctness by Construction", Edited book, Springer, Boston, MA, October 2010, Approx. 250 p. Hardcover, ISBN 978-1-4419-6399-4. Circuits and systems, Computer-aided engineering (CAD, CAE) and design
2010 S. Kundu, M. Ganai and C. Wang. "CONTESSA: concurrency testing augmented with symbolic analysis," International Conference on Computer Aided Verification (CAV'10), pages 127-131. Springer 2010. LNCS 6174.  
2010 S. Morozov, A. Maiti, P. Schaumont, "A Comparative Analysis of Delay Based PUF Implementations on FPGA," 6th International Symposium on Applied Reconfigurable Computing, March 2010. Physical Unclonable Functions (PUR), process variation, FPGA routing, Delay, arbiter, Ring oscillator, Butterfly
2010 S. Park, S.R. Anton, J.K. Kim, D.J. Inman, and D.S. Ha, "Instantaneous Baseline Structural Damage Detection using a Miniaturized Piezoelectric Guided Waves System," Korean Society of Civil Engineers (KSCE) Journal of Civil Engineering, vol. 14, no. 6, pp. 889-895, November 2010. Structural health monitoring, Piezoelectric sensor, Guided waves, Instantaneous baseline damage detection, Low power system
2010 S.-M. Lee, P. A. Araman, A. L. Abbott, and M. F. Winn, "Automated Grading, Upgrading, and Cuttings Prediction of Surfaced Dry Hardwood Lumber," Proceedings: 1st International Conference on Processing Technologies for the Forest and Bio-based Products Industries, Salzburg/Kuchl, Austria, Oct. 2010, pp. 198-200.  
2010 Sandesh Prabhakar and Michael S. Hsiao, "Multiplexed trace signal selection using non-trivial implication-based correlation," in Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March, 2010, pp. 697-704. Buffer storage, Circuit testing, Clocks, Computer bugs, Integrated circuit interconnections, Integrated circuit testing, Manufacturing, Multiplexing, Signal restoration, Silicon
2010 Saparya Krishnamoorthy, Michael S. Hsiao, and Loganathan Lingappan, "Tackling the path explosion problem in symbolic execution-driven test generation," in Proceedings of the IEEE Asian Test Symposium (ATS), December 2010, pp. 59-64. conflict analysis, software testing, symbolic execution
2010 Shravan Garlapati, Michael S. Hsiao, and Leyla Nazhandali, "Sharing of logic and test TSVs for testing of 3DICs," in Proceedings of the IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, November 2010.  
2010 Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla, "Power Aware High Level Synthesis of Hardware Coprocessors," Journal of Low Power Electronics, Vol. 6, No. 3, pp. 376-389 (2010). High level synthesis, Clock-gating, Transaction level modeling, Power estimation, power reduction, Power model
2010 V. Kahlon and C. Wang. "Universal causality graphs: a precise happens-before model for detecting bugs in concurrent programs," International Conference on Computer Aided Verification (CAV'10), pages 434-449. Springer 2010. LNCS 6174.  
2010 X. Guo, P. Schaumont, "Optimized System-on-Chip Integration of a Programmable ECC Coprocessor," ACM Transactions on Reconfigurable Technology and Systems (TRETS), 4(1), Article 6, December 2010. Algorithms, Design, Performance, Cryptography, Elliptic curves, system-on-chip, FPGA
2010 X. Guo, S. Huang, L. Nazhandali, P. Schaumont, "Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations", NIST 2nd SHA-3 Candidate Conference, Santa Barbara, CA, August 2010.  
2010 X. Guo, S. Huang, L. Nazhandali, P. Schaumont, "On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings," IACR ePrint 2010/536, October 2010.  
2010 Y. J. Kim, S.-M. Lee, J. S. Kim, and A. L. Abbott, "Motion Estimation with Massively Parallel Programming using CUDA," Proceedings: U.S.-Korea Conference on Green Technologies for a New World (UKC2010), Seattle, WA, Aug. 2010.  
2010 Yongxiang Peng, Yaling Yang, Xianliang Lu, and Xuyang Ding, "Coding-Aware Routing for Unicast Sessions in Wireless Mesh Networks", IEEE Globecom 2010.  
2010 Yujun Li and Yaling Yang, "Asymptotic Connectivity of Large-Scale Wireless Networks with a Log-Normal Shadowing Model", IEEE Vehicular Technology Conference (VTC 2010-Spring), 2010. Computer science, H infinity control, Large-scale systems, Radio communication, Radio propagation, Relays, Shadow mapping, Upper bound, Wireless networks, Wireless sensor networks
2010 Yujun Li and Yaling Yang, "Rules for Designing Routing Metrics for Greedy, Face and Combined-Greedy-Face Routing", IEEE Transactions on Mobile Computing, Volume 9, Issue 4, Pages: 582-595, April 2010 Geographic routing, consistency, delivery guarantee, loop freeness, routing algebra
2010 Z. Chen, A. Sinha, P. Schaumont, "Implementing Virtual Secure Circuit using a Custom-Instruction Approach," International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2010), Scottsdale, AZ, October 2010.  
2010 Z. Chen, P. Schaumont, "pSHS: A Scalable Parallel Software Implementation of Montgomery Multiplication for Multicore Systems," Design, Automation and Test in Europe (DATE 2010), March 2010. Clocks, Computer architecture, Delay, Multicore processing, Parallel processing, Parallel programming, Prototypes, Public key cryptography, Throughput, Topology
2010 Z. Chen, P. Schaumont, "Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore," IACR ePrint Archive 2010/272, April 2010.  
2010 Zhenhua Feng and Yaling Yang, "Throughput Analysis of Secondary Networks in Dynamic Spectrum Access Networks", IEEE Infocom 2010 Workshop on Cognitive Wireless Communications and Networking, 2010 Analytical models, Cognitive radio, Communications Society, Game theory, Interference, Peer to peer computing, Performance analysis, Radio transmitters, Resource management, Throughput
2009 A. B. MacKenzie, J. H. Reed, P. Athanas, C. W. Bostian, R. M. Buehrer, L. A. DaSilva, S. Ellingson, Y. T. Hou, M. Hsiao, J. Park, C. Patterson, S. Raman, and C. da Silva, "Cognitive Radio and Networking Research at Virginia Tech," Proceedings of the IEEE, Vol. 97, No. 4, Apr. 2009, pp. 660-688. Automatic modulation classification, cognitive networks, cognitive radio, dynamic spectrum access, game theory, genetic algorithms, multiple-input multiple-output (MIMO), radio-frequency integrated circuit design, software defined radio, spectrum sensing
2009 A. Bell, S. Raman, A. MacKenzie, P. Plassmann, C. Wyatt, L. DaSilva, L. Nazhandali, M. Agah, "Increasing the Enrollment, Retention and Satisfaction of First-Year Students in Electrical Engineering, Computer Engineering, and Computer Science," ASEE Annual Conference, Austin, TX, June 14-17, 2009.  
2009 A. Maiti, P. Schaumont, "Impact and Compensation of Correlated Process Variations on Ring Oscillator Based PUF," poster presentation, 17th International Symposium on Field Programmable Gate Arrays (FPGA 2009), February 2009.  
2009 A. Maiti, P. Schaumont, "Improving the Quality of a Physical Unclonable Function using Configurable Ring Oscillators," 19th International Conference on Field Programmable Logic and Applications (FPL 2009), September 2009. Application software, Field programmable gate arrays, Frequency, Hamming distance, Hardware, Manufacturing processes, Physics computing, Ring oscillators, Silicon, Working environment noise
2009 A. Maiti, R. Nagesh, A. Reddy, P. Schaumont, "Physical Unclonable Function and True Random Number Generator: a Compact and Scalable Implementation," 19th Great Lakes Symposium on VLSI (GLSVLSI 2009), May 2009. TRNG, Ring oscillators (RO), jitter, PUF, FPGA, Scalable, Macro
2009 Ahuja, S.; Gurumani, S.T.; Spackman, C.; Shukla, S.K.;, "Hardware Coprocessor Synthesis from an ANSI C Specification," IEEE Design & Test of Computers, vol.26, no.4, pp.58-67, July-Aug. 2009. ANSI C, ASIC, C2R methodology, ESL, FPGA, Verilog, design and test, high-level synthesis, power reduction, verification
2009 Ahuja, S.; Mathaikutty, D.A.; Lakshminarayana, A.; Shukla, S.;, "Accurate power estimation of hardware co-processors using system level simulation," IEEE International SOC Conference, 2009, Dublin, Ireland, pp.399-402, 9-11 Sept. 2009. Automata, Computational modeling, Coprocessors, Energy consumption, Energy management, Hardware, Power system management, Power system modeling, System-level design, System-on-a-chip
2009 Ahuja, S.; Shukla, S.;, "MCBCG: Model Checking Based Sequential Clock-Gating," IEEE International High Level Design Validation and Test Workshop (HLDVT), San Francisco, CA, pp.20-25, 4-6 Nov. 2009. Automation, CMOS logic circuits, CMOS technology, Clocks, Design optimization, Energy consumption, Optimization methods, Personal digital assistants, Pipeline processing, Registers
2009 B. Bahrak, A. Deshpande, and J. Park, "A policy reasoner for policy-based dynamic spectrum access," SDR '09 Technical Conference and Product Exposition, Dec. 2009.  
2009 Bijoy A. Jose, Bin Xue and Sandeep K. Shukla, "An analysis of the composition of synchronous systems," Fourth International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design (FMGALS 2009), Nice, France, Apr., 2009, Elsevier Electronic Lecture Notes in Theoretical Computer Science, Elsevier Publishers. Synchronous Programming Model, Polychrony, SIGNAL, endochrony, isochrony, Globally Asynchronous Locally Synchronous Systems, Unidirectional Isochrony
2009 Bijoy A. Jose, Bin Xue, Sandeep K. Shukla, and Jean-Pierre Talpin, "Programming models for Multi-Core Embedded Software," Book Chapter in "Multi-Core Embedded Systems", CRC Press, Taylor & Francis, London 2009.  
2009 Bin Xue and Sandeep K. Shukla, "Modeling and Analyzing the Implementation of Latency Insensitive Protocols using Polychrony Framework," Fourth International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design (FMGALS'09), Nice, France, Apr., 2009., Elsevier Electronic Lecture Notes in Theoretical Computer Science, Elsevier Publishers. latency-insensitive protocols, SIGNAL language, endochrony, isochrony, synchronous data flow graph, clock hierarchy 
2009 Bin Xue; Shukla, S.K.;, "Analysis of scheduled Latency insensitive systems with periodic clock calculus," IEEE International High Level Design Validation and Test (HLDVT) Workshop, 2009, San Francisco, CA, pp.1-7, 4-6 Nov. 2009. Calculus, Centralized control, Clocks, Delay, Lips, Processor scheduling, Protocols, Signal design, Synchronization, Throughput
2009 Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Ann Reeves, Michael Minuth, Ryan Helfand, Todd Austin, Dennis Sylvester, David Blaauw, "Energy Efficient Subthreshold Processor Design," IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), Vol. 17, No. 8, August 2009, pgs. 1127 - 1137. $V_{rm min}$, Sensor networks, subthreshold design, ultra low power design
2009 C. Wang, S. Chaudhuri, A. Gupta, and Y. Yang. "Symbolic pruning of concurrent program executions," ACM International Symposium on Foundations of Software Engineering (FSE'09), pages 23-32. August 2009. Amsterdam, The Netherlands. Concurrency, Partial order reduction, Pruning, SAT
2009 C. Wang, S. Kundu, M. Ganai, and A. Gupta. "Symbolic predictive analysis of concurrent programs," International Symposium on Formal Methods (FM'09), pages 256-272. Springer 2009. Lecture Notes in Computer Science 5850.  
2009 Chewoo Na and Yaling Yang, "MRSD: Multirate-based Service Differentiation for the IEEE 802.15.4 Wireless Sensor Network," IEEE Global Telecommunications Conference (Globecom), 2009. Adaptive control, Algorithm design and analysis, Collision avoidance, Multiaccess communication, Object detection, Programmable control, Scheduling algorithm, Time division multiple access, Video surveillance, Wireless sensor networks
2009 Chuan Han and Yaling Yang, "Compatibility between Optimal Tree-based Broadcast Routing and Metric Design," IEEE Global Telecommunications Conference (Globecom), 2009. Broadcasting, Chaos, Degradation, Delay effects, Energy consumption, Network topology, Performance loss, Routing protocols, Tree graphs, Unicast
2009 Chuan Han and Yaling Yang, "Proactive Attacker Localization in Wireless LAN," ACM Computer Communication Review, Vol. 39, Issue 2, pp 27-33, April 2009. Secure localization, wireless LAN
2009 Chuan Han and Yalng Yang, "Proactive attacker localization in WLAN," ACM Mobile Computing and Communications Review, Vol. 13, Issue 1, pp. 36-39, POSTER SESSION: MOBICOM 2008 poster abstracts, January 2009.  
2009 D. A. Mathaikutty and S. K. Shukla, "Meta-Modeling Driven IP Reuse for System-on-Chip Integration and Microprocessor Design", Artech House 2009. Pages. 330, Hardbound. ISBN 978-1-59693-424-5.  
2009 D. Zhou, J.K. Kim, D.S. Ha, J.D. Quesenberry, and D.J. Inman, “A System Approach for Temperature Dependency of Impedance-Based Structural Health Monitoring,” SPIE International Symposium on Smart Structures and Materials & Nondestructive Evaluation and Health Monitoring, Vol. 7293, 72930U-1 (10 pages), March 2009. structural health monitoring, SHM, impedance based method, temperature dependency, piezoelectric
2009 D. Zhou, J.K. Kim, J.-L.K. Bilé, A.B. Shebi, D.S. Ha, and D.J. Inman, “Ultra Low-Power Autonomous Wireless Structural Health Monitoring Node,” International Workshop on Structural Health Monitoring, pp. 797-804, September 2009.  
2009 Edgar G. Daylight, Sandeep K. Shukla, "On the Difficulties of Concurrent-System Design, Illustrated with a 2×2 Switch Case Study," In Proc. Of Formal Methods Conference (FM 2009): Eindhoven, Netherlands, pp.273-288, Springer. Formal specification languages, Local reasoning, Adaptability, Non-functional requirements 
2009 Edgar G. Daylight, Sandeep K. Shukla, Davide Sergio, "Expressing the Behavior of Three Very Different Concurrent Systems by Using Natural Extensions of Separation Logic," in the Proceedings of CoRR 0911.2034: (2009), Bologna, Italy, Electronic Lecture Notes on Theoretical Computer Science.  
2009 F. Belanger, R. Crossler, J. Hiller, J. Park, and M. Hsiao, "Children online privacy: Issues with parental awareness and control," in Annals of Emerging Research in Information Assurance, Security and Privacy Services, H.R. Rao and S. Upadhyaya (Eds.), Vol. 4, Emerald Group Publishing, 2009, pp. 311-333.  
2009 Harini Jagadeesan and Michael S. Hsiao, "A novel approach to design of user re-authentication systems," in Proceedings of the IEEE Conference on Biometrics: Theory, Applications and Systems (BTAS), September 2009, pp. 379-384. Behavioral Biometrics, interaction ratio, k-Nearest neighbor, neural networks, statistical analysis, user re-authentication
2009 J. Park, K. Bian, and R. Chen, "Cognitive Radio Network Security," Chapter 15 in Cognitive Radio Communications and Networks: Principles and Practice, A. Wyglinski, M. Nekovee, and T. Hou (Eds.), Elsevier, Dec. 2009.  
2009 J.K. Kim, D. Zhou, D.S. Ha, and D.J. Inman, “A Practical System Approach for Fully Autonomous Multi-Dimensional Structural Health Monitoring,” SPIE International Symposium on Smart Structures and Materials & Nondestructive Evaluation and Health Monitoring, Vol. 7292, 72921L-1 (10 pages), March 2009. structural health monitoring, structural damage detection, impedance method, Lamb wave, wave propagation method, digital signal processor, discrete wavelet transform
2009 J.K. Kim, D. Zhou, D.S. Ha, and D.J. Inman, “A Structural Health Monitoring System for Self-repairing,” SPIE International Symposium on Smart Structures and Materials & Nondestructive Evaluation and Health Monitoring, Vol. 7295, 729512-1 (8 pages), March 2009. structural health monitoring, impedance method, PZT, self-repairing, shape memory alloy
2009 James C.-M. Li and Michael S. Hsiao, "Fault Simulation and Test Generation," book chapter in Electronic Design Automation: Synthesis, Verification, and Test, edited by Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Cheng, 978-0123743640, Morgan Kaufmann, San Francisco, CA, pp. 851-917, 2009.  
2009 Jose, B.A.; Pribble, J.; Stewart, L.; Shukla, S.K.;, "EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applications," Specification & Design Languages, 2009. FDL 2009. Forum on, Nice, France, pp.1-6, 22-24 Sept. 2009. Application software, Clocks, Debugging, Design methodology, Equations, Flow graphs, Network synthesis, Software safety, Software tools, Synchronous generators
2009 J-S. Lee, and D.S. Ha, "FleXilicon Architecture and Its VLSI Implementation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 8, pp. 1021-1033, August 2009. Array processing, loop-level parallelism, reconfigurable architecture, system-on-chip (SOC)
2009 K. Bian and J. Park, "A Coexistence-Aware Spectrum Sharing Protocol for 802.22 WRANs," International Conference on Computer Communications and Networks (ICCCN '09), San Francisco, USA, Aug. 2009. Base stations, Chromium, Cognitive radio, Interference, Microphones, Resource management, Switches, TV broadcasting, Wireless application protocol, Wireless networks
2009 K. Bian and J. Park, "Addressing the hidden incumbent problem in 802.22 networks," SDR '09 Technical Conference and Product Exposition, Dec. 2009.  
2009 K. Bian, J. Park, and R. Chen, "A Quorum-based Framework for Establishing Control Channels in Dynamic Spectrum Access Networks," 15th ACM Annual International Conference on Mobile Computing and Networking (MobiCom 2009), Sep. 2009, Beijing, China. Control channel, dynamic spectrum access, channel hop-ping, quorum system, medium access control, cognitive radio
2009 K. Bian, J. Park, M. Hsiao, F. Belanger, and J. Hiller, "Evaluation of Online Resources in Assisting Phishing Detection," IEEE/IPSJ International Symposium on Applications and the Internet (SAINT), Seattle, USA, July 2009, pp. 30-36. Application software, Finance, Information systems, Insurance, Internet, Uniform resource locators, World Wide Web
2009 M. B. Henry and L. Nazhandali, "Hybrid super/subthreshold design of a low power scalable-throughput FFT architecture," volume 5409 of Lecture Notes in Computer Science, pages 278-292, Springer Berlin / Heidelberg, 2009.  
2009 M. Gora, A. Maiti, P. Schaumont, "A Flexible Design Flow for Software IP Binding in Commodity FPGA," IEEE Symposium on Industrial Embedded Systems (SIES 2009), July 2009. FPGA, Intellectual Property, Physical Unclonable Functions, Security Applications, Software Binding
2009 M.B. Henry, S. Griffin, and L. Nazhandali, "Fast simulation framework for subthreshold circuits," IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May 2009, pgs 2549-2552. Analytical models, Batteries, Circuit simulation, Delay effects, Delay estimation, Energy consumption, Performance evaluation, Prototypes, Timing, Voltage
2009 Maheshwar Chandrasekar and Michael S. Hsiao, "Diagnostic test generation for silicon diagnosis with an incremental learning framework based on search state compatibility," in Proceedings of the IEEE High Level Design Validation and Test (HLDVT) Workshop, pp. 68-75, November 2009. Automatic test pattern generation, Automatic testing, Circuit faults, Circuit testing, Electrical fault detection, Engines, Failure analysis, Fault detection, Silicon, Test pattern generators
2009 Maheshwar Chandrasekar and Michael S. Hsiao, "Search state compatibility and learning for state space exploration," in TECHCON, September 2009.  
2009 Mainak Banga and Michael S. Hsiao, "A novel sustained vector technique for the detection of hardware Trojans," in Proceedings of the IEEE International VLSI Design Conf., January, 2009, pp. 327-332. Power profile , Side-channel analysis , Torjan
2009 Mainak Banga and Michael S. Hsiao, "VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs," in Proceedings of the IEEE Hardware-Oriented Security and Trust (HOST) Workshop, July 2009, pp. 104-107. Benchmark testing, Circuit testing, Electrical fault detection, Fabrication, Fault detection, Information security, Integrated circuit testing, Logic design, MOS devices, Voltage
2009 Michael B. Henry, Leyla Nazhandali, "Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture," Transactions on HiPEAC: Volume 4, Issue 2, 2009, pgs. 175-194.  
2009 Michael S. Hsiao and Mainak Banga, "Kiss the scan goodbye: a non-scan architecture for high coverage, low test data volume and low test application time," in Proceedings of the IEEE Asian Test Symposium (ATS), November 2009, pp. 225-230. DFT, Scan Architecture
2009 Min Li and Michael S. Hsiao, "An ant colony optimization technique for abstraction-guided state justification," in Proceedings of the IEEE International Test Conference (ITC), November 2009. Ant colony optimization, Automatic test pattern generation, Circuit testing, Computational modeling, Computer simulation, Costs, Engines, Evolutionary computation, Genetic algorithms, Optimization methods
2009 Min Li, Yexin Zheng, Michael S. Hsiao, and Chao Huang, "Reversible Logic Synthesis Through Ant Colony Optimization," in Proceedings of the IEEE Design Automation and Test in Europe (DATE) Conference, April 2009, pp. 307-310. Ant colony optimization, Boolean functions, Chaos, Circuit synthesis, Energy dissipation, Logic circuits, Logic design, Nanotechnology, Quantum computing, Search problems
2009 N. Kong, A. Davoudi, M. Hagen, E. Oettinger, M. Xu, D.S. Ha, and F.C. Lee, "Automated System Identification of Digitally-Controlled Multi-phase DC-DC Converters," Applied Power Electronics Conference and Exposition (APEC), pp. 259-263, February 2009. DC-DC converters , digital control , system identification
2009 Nannan He and Michael S. Hsiao, "An efficient path-oriented bit-vector encoding width computation algorithm for bit-precise verification," in Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), April 2009, pp. 1602-1607. Acceleration, Controllability, Data analysis, Encoding, Equations, Formal verification, Hardware, Helium, Observability, Scalability
2009 P. Schaumont, A.K. Jones, S. Trimberger, "Guest Editors' Introduction to Security in Reconfigurable Systems Design," ACM Transactions on Reconfigurable Technology and Systems (TRETS), March 2009.  
2009 S. Morozov, A. Maiti, P. Schaumont, "A Comparative Analysis of Delay Based PUF Implementations on FPGA," IACR ePrint Archive 2009/629, December 2009. Physical Unclonable Functions (PUF), process variation, FPGA routing, delay, arbiter, ring oscillator, butterfly
2009 S. Park, S.R. Anton, D.J. Inman, J.K. Kim, and, D.S. Ha, “Instantaneous Baseline Damage Detection Using a Low Power Guided Waves System,” International Workshop on Structural Health Monitoring, pp. 505-512, September 2009.  
2009 S. S. Ravi and Sandeep Shukla eds, "Fundamental Problems in Computing: Essays in Honor of Daniel J. Rosenkrantz", Edited Book, Springer, Boston, MA, May, 2009, Approx. 350 p., Hardcover, ISBN: 978-1-4020-9687-7.  
2009 S. Xiao, J. Park, and Y. Ye, "Tamper Resistance for Software Defined Radio Software," IEEE Computer Software and Applications Conference (COMPSAC), July 2009. Application software, Computer applications, Cryptography, Electric resistance, Frequency modulation, Protection, Security, Software performance, Software radio, USA Councils
2009 S. M. Lee, A. L. Abbott, P. A. Araman, and M. F. Winn, "Automated Grading, Upgrading, and Cuttings Prediction of Surfaced Dry Hardwood Lumber," Proceedings: 6th International Symposium on Image and Signal Processing and Analysis (ISPA), Salzburg, Austria, Sept. 2009, pp. 371-376. Automation , Cameras, Design engineering, Fatigue, Humans, Life estimation, Prototypes, Sawing machines, System testing, US Department of Agriculture
2009 S. R. Anton, A. Erturk, N. Kong, D.S. Ha, and D.J. Inman, “Self-Charging Structures Using Piezoceramics and Thin-Film Batteries,” ASME Conference on Smart Materials, Adaptive Structures and Intelligent Systems, SMASIS2009-1368, (12 pages), September 2009.  
2009 Sandesh Prabhakar and Michael S. Hsiao, "Using non-trivial logic implications for trace buffer-based silicon debug," in Proceedings of the IEEE Asian Test Symposium (ATS), November 2009, pp. 131-136. Forward Learning, Logic implication, Silicon debug, State Restoration, Trace-signal selection
2009 Sangiovanni-Vincentelli, A.; Guang Yang; Shukla, S.K.; Mathaikutty, D.A.; Sztipanovits, J.;, "Metamodeling: An Emerging Representation Paradigm for System-Level Design," IEEE Design & Test of Computers, vol.26, no.3, pp.54-69, May-June 2009. IP reuse, MoC, design and test, metamodeling, models of computation, platform-based design
2009 Singh, Gaurav; Schwartz, Jacob B.; Shukla, Sandeep K, "A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent Action-Oriented Specifications," Journal of Low Power Electronics, Volume 5, Number 2, August 2009, pp. 135-144(10). High-level synthesis, CAOS (Concurrent Action-Oriented specifications), Peak power, Formal verification
2009 Sumit Ahuja, Deepak A. Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar, "Power estimation methodology for a high-level synthesis framework," 10th International Symposium on Quality of Electronic Design (ISQED), pp.541-546, San Jose, CA, 2009. High-level synthesis, power estimation, register transfer level, system level, vectorless
2009 Swapneel Donglikar, Mainak Banga, Maheshwar Chandrasekar, and Michael S. Hsiao, "Fast circuit topology based method to configure the scan chains in Illinois scan architecture," in Proceedings of the IEEE International Test Conference (ITC), November 2009. Automatic test pattern generation, Broadcasting, Circuit faults, Circuit testing, Circuit topology, Computer architecture, Costs, Electrical fault detection, Fault detection, Flip-flops
2009 V. Kahlon, C. Wang, and A. Gupta. "Monotonic partial order reduction: an optimal symbolic POR technique," International Conference on Computer Aided Verification (CAV'09), pages 398-413. Springer 2009. Lecture Notes in Computer Science 5643.  
2009 Vignesh Vivekraja, Leyla Nazhandali, "Circuit-Level Techniques for Reliable Physically Uncloneable Functions," IEEE International Workshop on Hardware-Oriented Security and Trust (HOST 2009), San Francisco, CA, USA, July 2009, pgs 30-35. Circuit testing, Cloning, Hospitals, Radio frequency, Radiofrequency identification, Random processes, Reproducibility of results, Ring oscillators, Voltage, Voltage-controlled oscillators
2009 X. Guo, J. Fan, P. Schaumont, I. Verbauwhede, "Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security," Proc. of the IACR Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009), September 2009.  
2009 X. Guo, P. Schaumont, "Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA based SoC Platform," 5th International Workshop on Applied Reconfigurable Computing (ARC2009), LNCS5453, pp. 169-180, Springer Verlag, March 2009.  
2009 X. Guo, P. Schaumont, "Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage," Design, Automation and Test in Europe (DATE2009), April 2009. Area measurement, Communication system control, Computer architecture, Coprocessors, Design optimization, Distributed control, Elliptic curve cryptography, Field programmable gate arrays, Hardware, Prototypes
2009 Y. Yang, X. Chen, G. Gopalakrishnan, and C. Wang. "Automatic discovery of transition symmetry in multithreaded programs using dynamic analysis," SPIN Workshop on Model Checking Software (SPIN'09), pages 279-295. Springer 2009. Lecture Notes in Computer Science 5578. Software engineering, Programming languages, compliers, interpreters, Logic and meanings and programs
2009 Yujun Li, Yaling Yang and Xianliang Lu, "Routing Metric Designs for Greedy, Face and Combined Greedy-Face Routing", IEEE Infocom 2009 Algebra, Communications Society, Computer science, Design engineering, Global Positioning System, Peer to peer computing, Routing protocols, Switches, USA Councils, Wireless networks
2009 Z. Chen, P. Schaumont, "Early Feedback on Side-Channel Risks with Accelerated Toggle-Counting," Proc. IEEE Workshop on Hardware Oriented Security and Trust (HOST 2009), July 2009. Fast Toggle Count, High-level Glitch Model, High-level Simulation, Side-Channel Attack
2009 Z. Chen, P. Schaumont, "Side-channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects," 3th International Conference on Information Security and Assurance (ISA 2009), June 2009. Computer communication networks, Computer systems organization and communication networks, Data structures, cryptology and information theory, Data encryption, System performance and evaluation, Coding and information theory
2009 Z. Chen, R. Nagesh, A. Reddy, P. Schaumont, "Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering," IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2009), May 2009. Circuits, Event detection, Field programmable gate arrays, Fingers, Frequency, Monitoring, Protection, Sensor phenomena and characterization, Temperature sensors, Thermal sensors
2009 Z. Yang, C. Wang, A. Gupta, and F. Ivancic. "Model checking sequential software programs via mixed symbolic analysis," ACM Transactions on Design Automation of Electronic Systems (TODAES), 13(1): 2009. Verification, model checking, Reachability analysis, Image computation, Binary decision diagram, Presburger arithmetic, Composite symbolic formula
2009 Zhenhua Feng and Yaling Yang, "Joint Transport, Routing and Spectrum Sharing Optimization for Wireless Networks with Frequency-Agile Radios", IEEE Infocom 2009 Algorithm design and analysis, Bandwidth, Bonding, Design optimization, Frequency, Prototypes Radio spectrum management, Routing, Utility programs, Wireless networks
2009 Zhenhua Feng and Yaling Yang, "Two Phase Spectrum Sharing for Frequency-Agile Radio Networks," IEEE International Conference on Communication (ICC), 2009.  
2009 Sumit Ahuja, Deepak A. Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla, "SCOPE: Statistical Regression Based Power Models for co-Processors Power Estimation", Journal of Low Power Electronics, Vol.5, No.4, pp.407-415, 2009. System-on-chip, Power estimation, finite state machine with datapath (FSMD), Statistical model, register transfer level (RTL), Co-processor
2008 Ahuja, S.; Mathaikutty, D.A.; Shukla, S.;, "Applying Verification Collaterals for Accurate Power Estimation," Ninth International Workshop on Microprocessor Test and Verification (MTV '08), Austin, TX, pp.61-66, 8-10 Dec. 2008. assertions, high-level synthesis, power estimation, system-level, system-on-chip, verificaiton collaterals
2008 Ankur Parikh and Michael S. Hsiao, "On dynamic switching of navigation for semi-formal design validation," Proceedings of the IEEE High Level Design Validation and Test (HLDVT) Workshop, pp. 41-48, November 2008. Analytical models, Circuits, Computational modeling, Computer simulation, Concrete, Hardware, Navigation, Scalability, State-space methods, Switches
2008 Bijoy A. Jose, Hiren D. Patel Sandeep K. Shukla, and Jean-Pierre Talpin, "Generating Multi-Threaded code from Polychronous Specifications," Proceedings of the Third International Workshop on Model-driven High-level Programming of Embedded Systems (SLA++P), Budapest, Hungary, April 2008. Synchronous programming model, polychrony, SIGNAL, Multi-core, Multi-threading, embedded software, Synthesis
2008 Bijoy A. Jose, Sandeep K. Shukla, Hiren D. Patel, and Jean-Pierre Talpin, "On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications," In the proceedings of the 6th ACM/IEEE International Conference on Formal Models and Methods in Co-Design (MEMOCODE), pp. 129-138, Anaheim, CA, June 2008. Application software, Concurrent computing, Formal specifications, Multicore processing, Operating systems, Programming profession, Signal generators, Software systems, Specification languages, Yarn
2008 C. Wang, Y. Yang, A. Gupta, and G. Gopalakrishnan. "Dynamic model checking with property driven pruning to detect race conditions," Intl. Symp. Automated Technology for Verification and Analysis (ATVA'08), pages 126-140. Springer 2008. LNCS 5311.  
2008 C. Wang, Z. Yang, V. Kahlon, and A. Gupta. "Peephole partial order reduction," International Conference on Tools and Algorithms for Construction and Analysis of Systems (TACAS'08), pages 382-396. Springer 2008. LNCS 4963.  
2008 Chewoo Na, Yaling Yang and Amitabh Mishra, "An optimal GTS scheduling algorithm for time-sensitive transactions in IEEE 802.15.4 networks," Elsevier Computer Networks, Volume 52, Issue 13, pp 2543-2557, September 2008. GTS, Scheduling, LR-WPAN, Schedulability, EDF
2008 Chuan Han, Jun Wang, Yaling Yang and Shaoqian Li, "Addressing the Control Channel Design Problem: OFDM-based Transform Domain Communication System in Cognitive Radio," Elsevier Computer Networks, Vol. 52/4, pp 795-815, March 2008. Cognitive radio, Control message transmission, Interleaved OFDM-base TDCS
2008 Coker, A.; Taylor, V.; Bhaduri, D.; Shukla, S.; Raychowdhury, A.; Roy, K., "Multijunction Fault-Tolerance Architecture for Nanoscale Crossbar Memories," Nanotechnology, IEEE Transactions on, vol.7, no.2, pp.202-208, March 2008. Crossbar nanomemories, fault tolerance, molecular electronics, nanoelectronics, reliability
2008 D. Bhaduri, S. K. Shukla, H. Quinn, P. Graham, and M. Gokhale, "Design and Analysis of Fault-Tolerant Molecular Computing System." Chapter 14 in Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability Series: Frontiers in Electronic Testing, Vol. 37, Tehranipoor, Mohammad (Ed.), ISBN 978-0-387-74746-0, Springer, 2008.  
2008 F. Yu, C. Wang, A. Gupta, and T. Bultan. "Modular verification of web services using efficient symbolic encoding and summarization," ACM International Symposium on Foundations of Software Engineering (SIGSOFT '08 / FSE-16), pages 192-202. ACM 2008. Verification, Modular verification, Summarization, BPEL
2008 Gaurav Singh and Sandeep K. Shukla. "Verifying Compiler Based Refinement of Bluespec Specifications using the SPIN Model Checker" 15th International SPIN Workshop on Model Checking (SPIN), Los Angeles, CA, USA, Springer Lecture Notes in Computer Science (LNCS), Vol. 5156, pp 250-269, August 2008. Formal verification, Hardware designs, Bluespac system verilog (BSV), SPIN model checker
2008 H. D. Patel and S. K. Shukla, "Model-driven Validation of SystemC Designs," in EURASIP Journal on Embedded Systems, Volume 2008, Article ID: 519474, 14 pages, April 2008.  
2008 H.D Patel and S. K. Shukla, "Ingredients for Successful System Level Automation and Design Methodology", Springer, Boston, MA, 2008. Pages. 208. Hardbound. ISBN 1-4020-8471-3. Electronic design automation (EDA), Electronic system level (ESL), system level design (SLD), system-on-chips
2008 Hong-Sik Kim, Sungho Kang, and Michael S. Hsiao, "A new scan architecture for both low power testing and test volume compression under SOC test environment," Journal of Electronic Testing: Theory and Applications, vol. 24, no. 4, August 2008, pp. 365-378.  System on a chip, scan testing, Low power testing, Test compression
2008 J. Kim, B. L. Grisso, J.K. Kim, D.S. Ha, and D.J. Inman, "Electrical Modeling of Piezoelectric Ceramics for Analysis and Evaluation of Sensory Systems,” IEEE Sensors Applications Symposium (SAS), pp. 122- 127, February 2008. Equivalent circuits, Modeling, PZT ceramics, Piezoelectric materials
2008 Janine S. Hiller, France Belanger, Michael S. Hsiao and Jung-Min Park, "POCKET protection," American Business Law Journal, vol. 45, no. 3, pp. 417-453, Fall, 2008.  
2008 K. B. Kochersberger, A. L. Lynn Abbott, D. L. Klomparens, A. A. Culhane, A. T. Sharkasi, and J. E. Smart, "Human Supervisory Control of an Autonomous VTOL using LIDAR and Stereovision," Proceedings: AUVSI Unmanned Systems North America, San Diego, June 2008.  
2008 K. Bian and J. Park, "Security Vulnerabilities in IEEE 802.22 (Invited Paper)," Fourth International Wireless Internet Conference (WICON), Nov. 2008. Design, Security, Standardization, IEEE 802.22, Incumbent coexistence, Self-coexistence
2008 K. Channakeshava, K. Bian, M. Hsiao, J. Park, R. Crossler, F. Belanger, P. Aggarwal, and J. Hiller, "On Providing Automatic Parental Consent over Information Collection from Children," International Conference on Security and Management (SAM '08), July 2008, pp. 196-202. COPPA, children's privacy, Verifiable parental consent
2008 Lei Fang and Michael S. Hsiao, "A fast approximation algorithm for MIN-ONE SAT," in Proceedings of the IEEE Design Automation and Test in Europe (DATE) Conference, March 2008, pp. 1087-1090. Approximation algorithms, Degradation, Electronic design automation and methodology
2008 Lei Fang and Michael S. Hsiao, "Bilateral testing of nano-scale fault-tolerant circuits," in Journal of Electronic Testing: Theory and Applications, vol. 24, no. 1-3, June 2008, pp. 285-296. Nanoelectronics, fault-tolerance, Bilateral fault model, ATPG
2008 Lei Fang and Michael S. Hsiao, "Boosting SAT solver performance via a new hybrid approach," Journal on Satisfiability, Boolean Modeling and Computation, vol. 5, June 2008, pp. 243-261. satisfiability, DPLL, WalkSAT, hybrid.
2008 M. Ganai, A. Gupta, F. Ivancic, V. Kahlon, W. Li, N. Papakonstantinou, S. Sankaranarayanan, and C. Wang. "Towards precise and scalable verification of embedded software," Design and Verification Conference (DVCon'08), 2008.  
2008 M. Gora, E. Simpson, P. Schaumont, "Intellectual Property Protection for Embedded Sensor Nodes," International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), July 2008.  
2008 Mahesh Chandrasekar and Michael S. Hsiao, "Minimum search state based learning: an efficient preimage computation technique," in TECHCON, September 2008.  
2008 Mainak Banga and Michael S. Hsiao, "A region based approach for the identification of hardware Trojans," in Proceedings of the IEEE Hardware-Oriented Security and Trust (HOST) Workshop, pp. 40-47, June 2008. Built-in self-test , Circuit testing , Costs , Fabrication , Foundries , Hamming distance , Hardware , Manufacturing processes , Monitoring , Viruses (medical)
2008 Mainak Banga, Maheshwar Chandrasekar, Lei Fang, and Michael S. Hsiao, "Guided test generation for isolation and detection of embedded Trojans in ICs," in Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, April 2008, pp. 363-366. Reliability, Security
2008 Mathaikutty, D., Patel, H., Shukla, S., and Jantsch, A. "EWD: A metamodeling driven customizable multi-MoC system modeling framework", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol.12, no.3, August 2008. Design, Languages, Verification, Metamodeling, Metamodel, MoC, functional language, denotational semantics, Interoperable modeling language, Heterogeneous system design, Ptolemy II, SystemC, ForSyDe
2008 Mathaikutty, D.A., Shukla, S.K. "Mining metadata for composability of IPs from SystemC IP library", Journal on Design Automation for Embedded Systems, Springer US, vol. 12, no. 1, pp. 63-94, 2008. Metadata, Metamodeling, Component composition framework, IP composition, Reflection, Introspection, Interoperability, Rype inference
2008 Mathaikutty, D.A., Patel, H.D., Shukla, S.K., and Jantsch, A. "SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system", Journal on Design Automation for Embedded Systems, Springer US, vol. 12, no. 1, pp. 1-30 Functional programming, Model of computation, Heterogeneity, Modeling fidelity, Modeling expressiveness
2008 Mathaikutty, D.A.; Kodakara, S.V.; Dingankar, A.; Shukla, S.K.; Lilja, D.J., "MMV: A Metamodeling Based Microprocessor Validation Environment," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.4, pp.339-352, April 2008. Architectural description language, metamodel, metamodeling, microprocessor, model-driven design and validation, refinement, validation collaterals
2008 Mathaikutty, D.A.; Shukla, S.K., "MCF: A Metamodeling-Based Component Composition Framework-Composing SystemC IPs for Executable System Models," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.7, pp.792-805, July 2008. Architectural template, component composition model, metamodel, metamodeling framework, partial specification
2008 Michael B Henry, Syed Imtiaz M Haider, Leyla Nazhandali, "A Low-Power Parallel Design of Discrete Wavelet Transform using Subthreshold Voltage Technology," International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Atlanta, GA, October 2008, pgs 235-244. wavelet, subthreshold, Parallel, Low power
2008 N. Kong, D.S. Ha, J. Li, and F.C. Lee, "Off-Time Prediction in Digital Constant On-Time Modulation for DC-DC Converters," International Symposium on Circuits and Systems (ISCAS), pp. 3270 - 3273, May 2008. Buck converters, DC-DC power converters, Digital control, Digital modulation, Frequency control, Prediction methods, Predictive models, Pulse modulation, Pulse width modulation converters, Switching frequency
2008 Nannan He and Michael S. Hsiao, "A new testability guided abstraction to solving bit-vector formula," in International Workshop on Bit-Precise Reasoning, July 2008. Controllability, Observability, Abstraction refinement
2008 Nannan He, Xueqi Cheng, and Michael S. Hsiao, "A new hybrid static/run-time secure memory access protection," in Proceedings of IEEE International Conf. on Technologies for Homeland Security, May 2008. Application software, Buffer overflow, Costs, Data security, Debugging, Instruments, Protection, Read-write memory, Runtime, Software systems
2008 Nikhil Kelkar, Yaling Yang, Dilip Shome and George Morgan, "A Business Model Framework for Dynamic Spectrum Access in Cognitive Networks," IEEE Global Telecommunications Conference (Globecom), 2008. Access protocols, Business communication, Cognitive radio, Companies, Finance, Intelligent networks, Investments, Radio frequency, Radio spectrum management, Transceivers
2008 P. Schaumont, "A Senior Level Course in Hardware/Software Codesign," IEEE Transactions on Education, Special Issue on Micro-Electronic Systems Education, 51(3):306-311, August 2008. Computer architecture, education, hardware design languages, logic design, modeling, simulation software
2008 P. Schaumont, "Hardware/Software Codesign is a Starting Point in Embedded Systems Architecture Education", ARTIST Workshop on Embedded Systems Education (WESE 2008), October 2008.  
2008 P. Schaumont, D. Hwang, "Turning Liabilities into Assets: Exploiting Deep-submicron CMOS Technology to Design Secure Embedded Circuits," IEEE International Symposium on Circuits and Systems (ISCAS 08), May 2008, Seattle. CMOS technology , Circuit synthesis, Communication system security, Cryptographic protocols, Cryptography, Embedded system, Identity-based encryption, Protection, Radiofrequency identification, Turning
2008 P. Schaumont, K. Asanovic, J. Hoe, "MEMOCODE 2008 Co-Design Contest", Sixth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2008), June 2008. Cryptography , Databases , Design methodology , Hardware , Indexes , Software performance , Software prototyping , Sorting , Statistics , Testing
2008 Patel, H.D.; Shukla, S.K., "On Cosimulating Multiple Abstraction-Level System-Level Models," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, no.2, pp.394-398, Feb. 2008. Bluespec, Interoperability, Modeling and simulation, Models of Computation, Simulation semantics, System Level Designs, SystemC, interoperability, modeling and simulation, models of computation, simulation semantics, system-level designs
2008 Peter Bokor, Sandeep Shukla, Andras Pataricza and Neeraj Suri, "Strengthened State Transitions for Complete Invariant Verification in Practical Depth-Induction", 3rd Workshop on Automated Formal Methods Workshop (AFM, in association with CAV 2008), Princeton, NJ, pages 31-41.  
2008 R. Chen, J. Park, and J. Reed, "Defense against primary user emulation attacks in cognitive radio networks," IEEE Journal on Selected Areas in Communications, vol. 26, no. 1, Jan. 2008, pp. 25-37. Chromium, Cognitive radio, Communication system security, Emulation, FCC, Interference, Radio spectrum management, Radio transmitters, White spaces, Wireless sensor networks
2008 R. Chen, J. Park, and K. Bian, "Robust distributed spectrum sensing in cognitive radio networks," 2008 IEEE INFOCOM Mini-Conference, Apr. 2008. Chromium, Cognitive radio, Decision support systems, FCC, Interference, Radio spectrum management, Robustness, Sequential analysis, TV, Wireless sensor networks
2008 R. Chen, J. Park, T. Hou, and J. Reed, "Toward secure distributed spectrum sensing in cognitive radio networks," IEEE Communications Magazine, Vol. 46, No. 4, April 2008, p.50 - 55. Base stations, Chromium, Cognitive radio, Data security, Decision support systems, Emulation, Fading, Mobile computing, Telecommunication network reliability, Wireless sensor networks
2008 R. Thirugnanam and D.S. Ha, "A Feasibility Study on Frequency Domain ADC for Impulse-UWB Receivers,” IEEE International Conference on Circuits & systems for Communications (ICCSC), pp. 516-520, May 2008. Band pass filters , Bandwidth , Baseband , Circuit simulation , Filter bank , Fourier series , Frequency domain analysis , Mathematical model , Narrowband , Sampling methods
2008 Robert E. Crossler, France Belanger, Janine S. Hiller, Jung-Min Park, Michael S. Hsiao, Karthik Channakeshava, Kaigui Bian, and Elizabeth Korbich, "Determinants of protection behaviors for online privacy of children," 39th Annual Meeting of The Decision Sciences Institute (DSI), pp. 1641-1647, November, 2008  
2008 S. Ahuja, G. Singh, D. Bhaduri, and S. Shukla, "Fault- and Defect-Tolerant Architectures for Nano-Computing," Chapter 10 in Nano- and Bio-Inspired Integrated Computing, eds. Mary Eshaghania, Wiley, 2008. Fault- and defect-tolerant architectures in nanocomputing, Fault tolerance through redundancy, Reliability evaluation of defect/fault-tolerant nanocomputing
2008 S. M. Lee, A. L. Abbott, and P. A. Araman, "Segmentation on Statistical Manifold with Watershed Transform," Proceedings: IEEE International Conference on Image Processing (ICIP 2008), San Diego, CA, Oct. 2008, pp. 625-628. Statistical manifold, segmentation, watershed transform
2008 Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, Dennis Sylvester, David Blaauw, “Exploring variability and performance in a sub-200-mV processor,” IEEE Journal of Solid-State Circuits, v 43, n 4, January, 2008, p 881-890. Low voltage, process variation, sensor network processing, subthreshold
2008 Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James C.-M. Li, Jiun-Lang Huang, and Ravi Apte, "On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs," in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTVS), pp. 143-151, October, 2008. Automatic Test Pattern Generation, Hybrid Single-Capture, One-Hot Single-Capture, Scan Testing, Simultaneous Single-Capture, Staggered Single-Capture
2008 Shrirang Yardi and Michael S.Hsiao, "Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads," in Proceedings of the IEEE International Conf. Computer Design (ICCD), pp. 583-590, October 2008. Algorithm design and analysis, Casting, Dynamic voltage scaling, Energy efficiency, Frequency, Hardware, Microprocessors, Performance analysis, Power engineering computing, Resource management
2008 Suhaib, S.; Mathaikutty, D.A.; Shukla, S.K., "A Trace-Based Framework for Verifiable GALS Composition of IPs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.9, pp.1176-1186, Sept. 2008. Asynchronous composition, correct-by-construction, globally asynchronous locally synchronous (GALS) design, single-activation, system-on-a-chip (SoC) validation, trace-based framework
2008 Syed Imtiaz M Haider, Leyla Nazhandali, "Utilizing Sub-threshold Technology for the Creation of Secure Circuits," IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, Washington, USA, 18-21 May 2008, pgs 3182-3185. Circuit noise , Cryptography, Electrical resistance measurement, Energy consumption, Hardware, Information security, Paper technology, Power measurement, Power system security, Threshold voltage
2008 Syed Suhaib Bijoy A. Jose, Deepak A. Mathaikutty, and Sandeep K. Shukla, "Formal Transformation of a KPN specification into a GALS implementation," In the proceedings of 11th Forum on Specification and Design Languages (FDL'08), pp. 84-89, Stuttgart, Germany, Sept., 2008. Clocks, Communication system control, Computational modeling, Computer architecture, Delay, Design methodology, Frequency synchronization, Joining processes, Protocols, Streaming media
2008 V. Chawla, R. Thirugnanam, D.S. Ha, and T.M. Mak, "Design of a Data Recovery Block for Communications over Power Distribution Networks of Microprocessors,” International Conference on Circuits & Systems for Communications (ICCSC), pp. 708-712, May 2008. Automatic testing, Circuit noise, Circuit testing, Frequency, Low-frequency noise, Microprocessors, Power line communications, Power systems, Programmable control, Routing
2008 Weixin Wu and Michael S. Hsiao, "Efficient design validation based on cultural algorithms," in Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), March 2008, pp. 402-407. Algorithm design and analysis, Analytical models, Circuit simulation, Computational modeling, Concrete, Costs, Cultural differences, Data mining, Design engineering, State-space methods
2008 Weixin Wu and Michael S. Hsiao, "Mining global constraints with domain knowledge for improving bounded sequential equivalence checking," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, January, 2008, pp. 197-201. Domain Constraint, Domain constraint, Mining, SAT, Multi-node Constraint, mining, multinode constraint, satisfiability (SAT)
2008 Weixin Wu and Michael S. Hsiao, "SAT-based state justification with adaptive mining of invariants," in Proceedings of the IEEE International Test Conf. (ITC), October 2008, 10 pages. Automatic test pattern generation, Circuit synthesis, Circuit testing, Databases, Logic arrays, Logic circuits, Observability, Packaging, Sequential circuits, State-space methods
2008 X. Guo, Z. Chen, P. Schaumont, "Energy and Performance Evaluation of an FPGA-based SoC Platform with AES and PRESENT Coprocessors", International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), July 2008.  
2008 Xueqi Cheng and Michael S. Hsiao, "Ant colony optimization directed program abstraction for software bounded model checking," in Proceedings of the IEEE International Conf. Computer Design (ICCD), pp. 46-51, October 2008. Ant colony optimization, Concrete, Context modeling, Explosions, Hardware, Power system modeling, Scalability, Software performance, Space exploration, State-space methods
2008 Xueqi Cheng and Michael S. Hsiao, "Simulation-directed invariant mining for software verification," in Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), March 2008, pp. 682-687.  
2008 Xueqi Cheng, Nannan He, and Michael S. Hsiao, "A new security sensitivity measurement for software variables," in Proceedings of IEEE International Conf. on Technologies for Homeland Security, May 2008. Buffer overflow, Buildings, Computer security, Electric variables measurement, Helium, Open source software, Programming profession, Protection, Software measurement, Software systems
2008 Yaling Yang and Jun Wang, "Design Guidelines for Routing Metrics in Multihop Wireless Networks," The 27th Conference on Computer Communications (Infocom), 2008. Algorithm design and analysis, Communications Society, Diversity reception, Guidelines, Mathematical model, Network topology, Routing protocols, Spread spectrum communication, Wireless communication, Wireless networks
2008 Yexin Zheng, Michael S. Hsiao, and Chao Huang, "SAT-based equivalence checking of threshold logic designs for nanotechnologies," in Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), April 2008, pp. 225-230.  
2008 Z. Chen, P. Schaumont, "Improving Secure Hardware Masking using an Equalization Technique", ACM Workshop on Embedded Systems Security (WESS 2008), October 2008.  
2008 Z. Chen, P. Schaumont, "Slicing Up a Perfect Hardware Masking Scheme", IEEE International Workshop on Hardware-Oriented Security and Trust (HOST), June 2008. Differential Power Analysis masking, Side-channel Attack, Slice
2008 Z. Chen, S. Morozov, P. Schaumont, "A Hardware Interface for Hashing Algorithms", ePrint IACR Archive, 2008/529, December 2008.  
2008 Zhenhua Feng and Yaling Yang, "Characterizing the Impact of Partially Overlapped Channel on the Performance of Wireless Networks", IEEE Global Telecommunications Conference (Globecom), 2008. Analytical models, Channel allocation, Frequency, Hardware, Interference, Network topology, Signal processing, Solid modeling, Telecommunication traffic, Wireless networks
2008 Zhenhua Feng and Yaling Yang, "How Much Improvement Can We Get From Partially Overlapped Channels?", IEEE Wireless Communications & Networking Conference (WCNC), 2008.  
2007 A. Patcha and J. Park, "An overview of anomaly detection techniques: existing solutions and latest technological trends," Computer Networks, Vol. 51, Issue 12, 2007, pp. 3448-3470. Survey, Anomaly detection, Machine learning, Statistical anomaly detection, Data mining
2007 A. Patcha and J. Park, "Network Anomaly Detection with Incomplete Audit Data," Computer Networks, Vol. 51, Issue 13, 2007, pp. 3935-3955. Network anomaly detection, Expectation–maximization algorithm, Sampling
2007 A. S. Abdallah, A. L. Abbott, and M. Abou El-Nasr, "A New Face Detection Technique using 2D DCT and Self Organizing Feature Map," Proceedings: International Conference on Computer, Information, and Systems Science, and Engineering, World Academy of Science, Engineering and Technology, vol. 21, Vienna, Austria, May 2007, pp. 15-19.  
2007 A. S. Abdallah, A. Lynn Abbott, and M. Abou El-Nasr, "Fusion of 2D-DCT and Edge Features for Face Detection with an SOM Classifier," Proceedings: International Conference on Applied Electronics (AE 2007), Pilsen, Czech Republic, Sept. 2007, pp. 3-8.  
2007 A. S. Abdallah, M. Abou El-Nasr, and A. L. Abbott, "A New Color Image Database for Benchmarking of Automatic Face Detection and Human Skin Segmentation Techniques," Proceedings: International Conference on Computer, Information, and Systems Science and Engineering, World Academy of Science, Engineering and Technology, vol. 20, Barcelona, Spain, April 2007, pp. 353-357.  
2007 Ahuja, S.; Mathaikutty, D.A.; Shukla, S.; Dingankar, A.;, "Assertion-Based Modal Power Estimation," MTV '07. Eighth International Workshop on Microprocessor Test and Verification, Austin, TX, pp.3-7, 5-6 Dec. 2007. Assertion, Mode-based design, Power Estimation, System-level
2007 Ankur Parikh, Weixin Wu, and Michael S. Hsiao, "Mining-guided state justification with partitioned navigation tracks," in Proceedings of the IEEE International Test Conference (ITC), Oct. 2007. Automatic test pattern generation, Circuit simulation, Circuit testing, Computational modeling, Concrete, Design engineering, Navigation, Sequential circuits, State-space methods, Target tracking
2007 Bhaduri, D.; Shukla, S.; Graham, P.; Gokhale, M., "Comparing Reliability-Redundancy Tradeoffs for Two von Neumann Multiplexing Architectures," IEEE Transactions on Nanotechnology, vol.6, no.3, pp.265-279, May 2007. Fault-tolerance, interconnect, majority, multiplexing, nanotechnology, noise, probabilistic model checking, probabilistic transfer matrices, probability, reliability
2007 Bhaduri, D.; Shukla, S.K.; Graham, P.S.; Gokhale, M.B., "Reliability Analysis of Large Circuits Using Scalable Techniques and Tools," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.54, no.11, pp.2447-2460, Nov. 2007. CMOS, Circuit, Scalable, Extensible Tool for Reliability Analysis (SETRA), computer-aided design (CAD), defects, methodologies, nanoscale, nanotechnology, probabilistic model checking (PMC), probability, reliability, scalability, techniques, tool
2007 Bin Li, Lei Fang, and Michael S. Hsiao, "Efficient power droop aware delay fault testing," in Proceedings of the IEEE International Test Conference (ITC), Oct. 2007. Circuit faults, Circuit testing, Delay effects, Fault diagnosis, Filters, Propagation delay, Rails, Switching circuits, Test pattern generators, Voltage
2007 C. Wang, A. Gupta, and F. Ivancic. "Induction in CEGAR for detecting counterexamples," International Conference on Formal Methods in Computer Aided Design (FMCAD'2007), pages 77-84. IEEE 2007. Austin, TX. Chaos, Computer bugs, Concrete, Design automation, Interpolation, National electric code, Pattern analysis, Performance analysis, Refining, Safety
2007 C. Wang, H. Kim, and A. Gupta. "Hybrid CEGAR: combining variable hiding and predicate abstraction," IEEE/ACM International Conference on Computer-Aided Design (ICCAD'07), pages 310-317. San Jose, CA. November 2007. Chaos, Concrete, Hardware, Laboratories, National electric code, Performance analysis, State-space methods, System-level design
2007 C. Wang, Z. Yang, A. Gupta, and F. Ivancic. "Using counterexamples for improving the precision of reachability computation with polyhedra," International Conference on Computer Aided Verification (CAV'07), pages 352-365. Springer 2007. LNCS 4590.  
2007 C. Wang, Z. Yang, F. Ivancic, and A. Gupta. "Disjunctive image computation for embedded software verification," ACM Transactions on Design Automation of Electronic Systems (TODAES) 12(2): Article No. 10, April 2007. ACM TODAES Best Journal Paper Award Model checking, reachability analysis, image computation, binary decision diagram, formal verification
2007 D. Bhaduri and S. K. Shukla, "Probabilistic Analysis of Self-Assembled Molecular Networks", Chapter 6 in Systems Self-Assembly: Multi-disciplinary Snapshots, N. Krasnogor, S. Gustafson, D. Pelta and J. Verdegay Eds., Elsevier Publishers, Series: Studies in Multi-disciplinarily, 2007.  
2007 D. Ha, P. Schaumont, "Replacing Cryptography with Ultra Wideband (UWB) Modulation in Secure RFID," IEEE International Conference on RFID 2007, Grapevine, TX, March 2007. Cryptography, Delay, Modulation coding, Narrowband, Passive RFID tags, Pulse modulation, RFID tags, Radiofrequency identification, Silicon, Ultra wideband technology
2007 Daylight, E.G.; Shukla, S., "Local Causal Reasoning of a Safety-Critical Subway System," 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign, MEMOCODE 2007. Nice, France, pp.83-84, May 30 2007-June 2 2007. Actuators, Computer errors, Design engineering, Formal specifications, Management training, Process design, Switches
2007 Debayan Bhaduri, Sandeep K. Shukla, Paul Graham, Maya Gokhale, "Scalable techniques and tools for reliability analysis of large circuits," VLSI Design 2007, pp. 705-710, In proc. of the International VLSI Design Conference, Bangalore India, January 2007. (Acceptance: 31%) Circuit analysis, Design automation, Integrated circuit reliability, Laboratories, Logic circuits, Logic gates, Probabilistic logic, Runtime, Scalability, Semiconductor device modeling
2007 Deepak A. Mathaikutty and S. K. Shukla. "MCF: A Metamodeling based Visual Component Composition Framework." Chapter 19 in Advances in Design and Specification Languages for Embedded Systems - Selected Contributions from FDL'06, Springer Verlag, 2007.  
2007 Deepak A. Mathaikutty and S. K. Shukla. "Mining Metadata for Composability of IPs from SystemC IP Library." Chapter 7 in Advances in Design and Specification Languages for Embedded Systems - Selected Contributions from FDL'06, Springer Verlag, 2007.  
2007 Deepak A. Mathaikutty, A. Dingankar and S. Shukla. "A Metamodeling based Framework for Architectural Modeling and Simulator Generation," Forum of Specification and Design Languages (FDL'07), Barcelona, Spain, September 2007, pp. 1-6.  
2007 Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar, "Design fault directed test generation for microprocessor validation," Proceedings of Design Automation and Test in Europe (DATE), pp. 761-766, Nice, France, April 2007 (Acceptance: 25%). Aerospace electronics, Computer bugs, Error correction, Fault detection, Logic, Microarchitecture, Microprocessors, Software systems, Software testing
2007 Duncan M. Walker and Michael S. Hsiao, "Delay Testing," book chapter in System-on-Chip Test Architectures, edited by Laung-Terng Wang, Charles E. Stroud, and Nur A. Touba, Morgan Kaufmann, San Francisco, CA, pp. 263-306, 2007.  
2007 E. D. de León, G. W. Flintsch, and A. L. Abbott, "Measuring the Uniformity of Hot-mix Asphalt Pavements with Digital Image Technology," Proceedings: 86th Annual Meeting of the Transportation Research Board, Washington, D.C., 2007.  
2007 E. Simpson, P. Yu, P. Schaumont, S. Ahuja, S. Shukla, "VT Matrix Multiply Design for MEMOCODE 07," Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007), Nice, France, 2007. Algorithm design and analysis, Computer architecture, Concurrent computing, Control system synthesis, Coprocessors, Delay, Design optimization, Field programmable gate arrays, Read-write memory, Runtime
2007 Gaurav Singh, Jacob B. Schwartz, Sumit Ahuja, Sandeep K. Shukla. "Techniques for Power-aware Hardware Synthesis from Concurrent Action Oriented Specifications." Journal of Low Power Electronics (JOLPE), Vol. 3, No. 2, Pages 156-166, August 2007. High-level synthesis, CAOS (Concurrent action Oriented Specifications), Dynamic power, Clock-gating, Operand isolation
2007 Gaurav Singh, Sandeep K. Shukla. "Algorithms for Low Power Hardware Synthesis from CAOS (Concurrent Action Oriented Specifications)," Special issue of International Journal of Embedded Systems (IJES) on Power/Energy/Thermal topics, 2007, Vol. 3, No. 1-2, pp. 83-92. behavioural synthesis, concurrent action-based specifications, low-power design, peak power, switching power, semantics, hardware design, power-aware computing
2007 Hiren D. Patel, Sandeep K. Shukla, "Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL," Proceedings of Design Automation and Test in Europe (DATE 2007), pp. 279-284, Nice, France, April 2007 (Acceptance: 25%). Computational modeling, Computer errors, Concurrent computing, Counting circuits, Discrete event simulation, Hardware design languages, High level synthesis, Impedance, Job shop scheduling, System-level design
2007 I. Verbauwhede, P. Schaumont, "Design Methods for Security and Trust," Design Automation and Test Conference in Europe (DATE 2007), Nice, France, April 2007. Circuits, Costs, Design methodology, Embedded computing, Embedded system, Hardware, Pervasive computing, Power system security, Protection, Protocols
2007 Irani, S., Shukla, S., and Gupta, R. "Algorithms for power savings," ACM Transactions on Algorithms, Vol. 3, No.4, Article No. 41, Nov. 2007. Power savings, Dynamic speed scaling, Online algorithms
2007 J. Djigbenou, and D.S. Ha, "Development and Distribution of TSMC 0.25 um Standard CMOS Library Cells, " International Conference on Microelectronic Systems Education, pp. 27-28, June 2007. Analog-digital conversion, Circuit simulation, Circuit synthesis, Hardware design languages, Libraries, Logic design, Multiplexing, Standards development, Telecommunication standards, Very large scale integration
2007 J. Djigbenou, T.V. Nguyen, C.W. Ren, and D.S. Ha, “Development of TSMC 0.25um Standard Cell Library,” IEEE Southeast Conference, pp. 566-568, March 2007.  
2007 J. H. Cha and A. L. Abbott, "Designing an Error Metric for Super-resolution Enhanced IR Passive Ranging," Proceedings: Infrared Imaging Systems: Design, Analysis, Modeling, and Testing XVIII, SPIE Defense & Security Symposium (DSS), vol. 6543, Orlando, FL, Apr. 2007, pp. 65430Y1-9. Passive ranging, Super-resolution reconstruction, stereo analysis, Sample-scene phasing
2007 J. Kim, B. L. Grisso, D. S. Ha, and D. J. Inman, “An All-Digital Low-Power Structural Health Monitoring System,” Conference on Technologies for Homeland Security, pp. 123-128, May 2007. Computerized monitoring, Energy consumption, Frequency conversion, Frequency measurement, Hardware, Impedance measurement, Power dissipation, Prototypes, Signal generators, Voltage
2007 J. Kim, B. L. Grisso, D. S. Ha, and D. J. Inman, “Digital Wideband Excitation Technique for Impedance-Based Structural Health Monitoring Systems,” International Symposium on Circuits and Systems (ISCAS), pp. 3566-3569, May 2007. Aging, Hardware, Impedance measurement, Mechanical sensors, Monitoring, Performance loss, Power dissipation, Prototypes, Sensor systems, Wideband
2007 J. Kim, B.L. Grisso, D.S. Ha, and D.J. Inman, "A system-On-Board Approach for Impedance-Based Structural Health Monitoring," SPIE International Symposium on Smart Structures and Materials & Nondestructive Evaluation and Health Monitoring, March 2007.  
2007 J. Li, Y. Qiu, Y. Sun, B. Huang, M. Xu, D. S. Ha, F. C. Lee, "High Resolution Digital Duty Cycle Modulation Schemes for Voltage Regulators," IEEE Applied Power Electronics Conference and Exposition, pp. 871-876, February 2007. High resolution DPWM, limit cycle oscillation, voltage regulator
2007 J. S. Hiller, F. Bélanger, P. Aggarwal, M. Hsiao, J. Park, R. Crossler, K. Channakeshava, and K. Bian, "COPPA, Parental Consent, and Website Compliance," Mid-Atlantic Academy of Legal Studies in Business, Mar. 23-24, 2007.  
2007 J. S. Lee, and D.S. Ha, “High Speed 1-bit Bypass Adder Design for Low Precision Additions,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1093-1096, May 2007. Adders, CMOS process, Circuits, Computer architecture, Electronic mail, Logic, Parallel processing, Reconfigurable architectures, Signal generators, Very large scale integration
2007 K. Bian and J. Park, "Segment-Based Channel Assignment in Cognitive Radio Ad Hoc Networks," Proc. of the International Conference on Cognitive Radio Oriented Wireless Networks and Communications (CrownCom 2007), Aug. 2007. Ad hoc networks, Chromium, Cognitive radio, Computer security, Delay, FCC, Information security, Radio spectrum management, Space technology, White spaces
2007 K. K. Bae, J. Park, and J. H. Reed, "An overview of cognitive radio research at Virginia Tech," 2007 US - Korea Conference on Science, Technology, and Entrepreneurship (UKC 2007), Aug. 2007. automatic modulation classification, Cognitive networks, Cognitive radio, Dynamic spectrum access, Game theory, Genetic algorithms, Multiple-input multiple-output (MIMO), Radio-frequency integrated circuit design, Software defined radio, spectrum sensing
2007 Lei Fang and Michael S. Hsiao, "A new hybrid solution to boost SAT solver performance," in Proceedings of the IEEE Design Automation and Test in Europe (DATE) Conference, April 2007, pp. 1307-1313. Application software, Artificial intelligence, Computer applications, Degradation, Electronic design automation and methodology, Performance analysis, Performance gain, Stochastic systems, Test pattern generators
2007 M. Chorzempa, J. Park, and M. Eltoweissy, "Key management for long lived sensor networks in hostile environments," Computer Communications, Vol. 30, Issue 9, June 2007, pp. 1964-1979. sensor networks, Key management, survivability, Clustering, security, Hostile environments
2007 M. Snow and J. Park, "Link Layer Traceback in Ethernet Networks," proc. of the IEEE Workshop on Local and Metropolitan Area Networks (LANMAN 2007), June 2007. Computer networks, Ethernet networks, IP networks, Internet, Local area networks, Protocols, Routing, Snow, Switches
2007 Maheshwar Chandrasekar and Michael S. Hsiao, "Efficient search space pruning for multi valued SAT based ATPG," in Proceedings of the IEEE European Test Symposium, May 2007, pp. 211-216.  
2007 Mathaikutty, D.A.; Ahuja, S.; Dingankar, A.; Shukla, S.;, "Model-driven test generation for system level validation," IEEE International High Level Design Validation and Test Workshop (HLVDT 2007). Irvine, CA, pp.83-90, 7-9 Nov. 2007. Automatic testing, Energy management, Machine components, Microprocessors, Software systems, Software testing, Synchronous generators, System testing, System-level design, System-on-a-chip
2007 Mathaikutty, D.A.; Shukla, S.K., "Type Inference for IP Composition," 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007), Nice, France, pp.61-70, May 30 2007-June 2 2007. Acceleration, Buildings, Contracts, Inference algorithms, Libraries, Modeling, Productivity, Software engineering, Space exploration, System-level design
2007 N. August, H.J. Lee, and D.S. Ha, "Enabling Distributed Medium Access Control for Impulse-Based Ultra Wideband Radios," IEEE Transactions on Vehicular Technology, Vol. 56, No. 3, pp. 1064-1075, May 2007. Ad hoc networks, carrier sense, medium access control (MAC), sensor networks, ultrawideband (UWB)
2007 Nannan He and Michael S. Hsiao, "Bounded model checking of embedded software in wireless cognitive radio systems," in Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct, 2007, pp. 19-24. Application software, Cognitive radio, Embedded software, Encoding, FCC, Hardware, Helium, Saturn, Scalability, Software tools
2007 P. Schaumont, "A Senior Level course in hardware-software codesign," IEEE International Conference on Microelectronic Systems Education (MSE 2007), San Diego, June 2007. Algorithm design and analysis, Application software, Computer architecture, Computer industry, Coprocessors, Design engineering, Field programmable gate arrays, Hardware, Signal design, Software design 
2007 P. Schaumont, A. Raghunathan, "Guest Editor's Introduction: Security and Trust in Embedded-Systems Design," IEEE Design and Test of Computers, Special Issue on Design and Test of ICs for Secure Embedded Computing, Vol.24, No.6, pp.518-520, November/December 2007. design, embedded systems, security, trust
2007 P. Schaumont, I. Verbauwhede, "Hardware/Software Codesign for Stream Ciphers," SASC (State of the Art of Stream Ciphers), Special workshop hosted by the ECRYPT Network of Excellence in Cryptology, Bochum, Germany, January 2007.  
2007 P. Schaumont, K. Tiri, "Masking and Dual-Rail Logic Don't Add Up," Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), September 2007.  
2007 P. Trisiripisal, S. M. Lee, and A. L. Abbott, "Iterative Image Coding using Hybrid Wavelet-based Triangulation," Proceedings: 13th International MultiMedia Modeling Conference (MMM 2007), Singapore, Jan. 2007, Lecture Notes in Computer Science, vol. 4351, Springer, pp. 309-321.  
2007 P. Yu, P. Schaumont, "Secure FPGA Circuits using Controlled Placement and Routing," IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), October 2007. Clocks, Fabrics, Field programmable gate arrays, Logic gates, Power demand, Routing, Table lookup
2007 Patel, H.D.; Shukla, S.K.; Bergamaschi, R.A., "Heterogeneous Behavioral Hierarchy Extensions for SystemC," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, no.4, pp.765-780, April 2007. Behavioral decomposition, SystemC, behavioral modeling, embedded system design, heterogeneous behavioral hierarchy, hierarchical finite state machine (HFSM), hierarchical synchronous data flow (SDF), models of computation (MoCs), simulation efficiency, structural modeling, system level designs
2007 Patel, H.D.; Shukla, S.K.;, "Model-driven Validation of SystemC Designs," 44th ACM/IEEE Design Automation Conference (DAC), San Diego, CA., pp.29-34, 4-8 June 2007. Abstract StateMachines, Design, Model-driven, Semantic model and simulation, Spec-Explorer, SystemC, Test case generation, Validation, Verification
2007 R. Chen, J. Park, and R. Marchany, "A divide-and-conquer strategy for thwarting distributed denial-of-service attacks," IEEE Transactions on Parallel and Distributed Systems, Vol. 18, No. 5, May 2007, pp. 577-588. Network-level security and protection
2007 R. E. Crossler, F. Bélanger, J. S. Hiller, P. Aggarwal, K. Channakeshava, K. Bian, J. Park, and M. Hsiao, "Parents and the Internet: Privacy Awareness, Practices, and Control," Proceedings of the America's Conference on Information Systems (AMCIS), Keystone, Colorado, Aug. 2007.  
2007 R. Thirugnanam, D.S. Ha, and T. M. Mak, "Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.153-158, May 2007. CMOS process, Circuit simulation, Circuit testing, Degradation, Impulse testing, Microprocessors, Power line communications, Power supplies, Programmable control, Ultra wideband technology
2007 R. Thirugnanam, D.S. Ha, and T. M. Mak, “On Channel Modeling for Impulse-Based Communications over a Microprocessor's Power Distribution Network,” IEEE International Symposium on Power Line Communications (ISPLC), pp. 355-359, March 2007. DFT , Microprocessor, Power distribution network, Power line communication
2007 S. K. Shukla, S. Suhaib, Deepak A. Mathaikutty and J-P Talpin. "On the Polychronous Approach to Embedded Software Design." In GM R&D Workshop on Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems, Springer Verlag, January 2007.  
2007 S. M. Lee, A. L. Abbott, and P. A. Araman, "Dimensionality Reduction and Clustering on Statistical Manifolds", Proceedings: IEEE Workshop on Component Analysis Methods for Classification, Clustering, Modeling, and Estimation Problems in Computer Vision, in conjunction with CVPR 2007, Minneapolis, MN, June 2007, pp. 1-7. Image segmentation, Image texture analysis, Level measurement, Parametric statistics, Pattern recognition, Principal component analysis, Probability density function, Probability distribution, Stochastic processes, Tensile stress
2007 Scott Hanson, Bo. Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, Dennis Sylvester, and David Blaauw, "Performance and variability optimization strategies in a sub-200mV, 3.5pJ/inst, 11nW subthreshold processor," IEEE Symposium on VLSI Circuits (VLSI-Symp), June 2007, pgs 152-153. body-bias, low power, subthreshold, variability
2007 Shrirang Yardi and Michael S. Hsiao, "Integrating validation and verification in the digital design curriculum," in Proceedings of the International Conference on Microelectronic Systems Education (MSE), June 2007, pp. 143-144. Combinational circuits, Debugging, Design engineering, Logic design, Logic devices, Programmable logic arrays, Programmable logic devices, Sequential circuits, Terminology, Testing
2007 Singh, G.; Shukla, S.K.;, "Model Checking Bluespec Specified Hardware Designs," Eighth International Workshop on Microprocessor Test and Verification (MTV), Austin, TX, pp.39-43, 5-6 Dec. 2007. Bluespec System Verilog(BSV), High-Level Synthesis, Model Checking, Spin
2007 Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja, "Model Based Test Generation for Microprocessor Architecture Validation," Proc. of the International VLSI Design Conference, pp. 465-472, Bangalore, India, January 2007. (Acceptance: 31%) Analytical models, Computer bugs, Cost function, Microprocessors, Natural languages, Product development, Testing, Time to market, Trademarks, Very large scale integration
2007 Syed Imtiaz M Haider, Leyla Nazhandali, "A Hybrid Code Compression Technique using Bitmask and Prefix Encoding with Enhanced Dictionary Selection," International Conference on Compilers, Architecture and Synthesis for Embedded Systems CASES, Salzburg, Austria, Sep. 30-Oct. 5, 2007, pgs 58-62.  
2008 Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, "Dataflow Architectures for GALS", Electronic Notes in Theoretical Computer Science (ENTCS), 200(1):33-50, February 2008. Post proceedings of In 3rd International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design (FMGALS'07), Nice, France, May 2007.  Kahn process networks, Globally asynchronous locally synchronous, Unbounded FIFO channels
2007 V. Chawla and D.S. Ha, "An Overview of Passive RFID," IEEE Applications & Practice, Supplement to IEEE Communications Magazine, Vol. 45, Issue 9, pp. 11-17, September 2007. Coils, Coupling circuits, Dipole antennas, Frequency, Loaded antennas, Magnetic fields, Passive RFID tags, Radiofrequency identification, Rectifiers, Reflector antennas
2007 Vishnu Vimjam and Michael S. Hsiao, "Explicit safety property strengthening in SAT-based induction," in Proceedings of the IEEE International VLSI Design Conf., January 2007, pp. 63-68. Binary decision diagrams, Computer bugs, Decision making, Engines, Induction generators, Logic design, Reachability analysis, Runtime, Safety, Writing
2007 Vishnu Vimjam, Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, and Kai Yang, "Using scan-dump values to improve functional-diagnosis methodology," in Proceedings of the IEEE VLSI Test Symposium, May, 2007, pp. 231-238. Automatic test pattern generation, Circuit faults, Circuit simulation, Circuit testing, Failure analysis, Fault diagnosis, Integrated circuit testing, Logic circuits, Logic testing, Performance evaluation
2007 Weixin Wu and Michael S. Hsiao, "Mining sequential constraints for pseudo-functional testing," Proceedings of the IEEE Asian Test Symposium (ATS), Oct. 2007, pp. 19-24. Application software, Automatic test pattern generation, Circuit faults, Circuit testing, Delay, Electrical fault detection, Fault detection, Sequential analysis, State-space methods, USA Councils
2007 Weixin Wu and Michael S. Hsiao, "Mining-guided sequential ATPG with partitioned navigation tracks for design validation," in TECHCON, September 2007.  
2007 Xiaoding Chen and Michael S. Hsiao, "An overlapping scan architecture for reducing both test time & test power by pipelining fault detection," in IEEE Transactions on VLSI Systems, vol. 15, no. 4, April 2007, pp. 404-412. Low-power testing, pipelining of fault detection, scan architecture, test application time reduction
2007 Xueqi Cheng, Nannan He, and Michael S. Hsiao, "Hybrid testing and verification techniques for a cognitive radio system," Proceedings of the International Conf. on Software Engineering and Applications (SEA), November 2007, pp. 240-245.  
2007 Y. Qiu, J. Li, M. Xu, D. S. Ha, F. C. Lee, "Proposed DPWM Scheme with Improved Resolution for Switching Power Converters," Applied Power Electronics Conference and Exposition (APEC), pp. 1588-1593, February 2007. Limit cycle oscillation, digital control, dual-clock DPWM
2007 Yaling Yang and Robin Kravets, "Throughput Guarantees for Multi-priority Traffic in Ad Hoc Networks'', Ad Hoc Networks, Vol. 5, No.2, pp.228-253, March 2007. Admission control, Bandwidth allocation, IEEE802.11, Ad hoc networks, QoS
2007 Yaling Yang, "Routing Metrics Design for Multihop Wireless Networks," Communication Networking Technology (CNT) Symposium under UKC (US-Korea Symposium), 2007 (invited paper)  
2007 Yaling Yang, Jun Wang and Robin Kravets, "Distributed Optimal Contention Window Control for Elastic Traffic in Single Cell Wireless LANs," IEEE/ACM Transaction on Networking, Vol. 15/6, December 2007. Dynamic bandwidth allocation, fairness, wireless LAN
2008 P. Schaumont, E. Simpson, P. Yu, "A Video Interface with End-point Security," Technical Report, Department of Electrical & Computer Engineering, Virginia Tech, January 2008.  
2010 N. Short, A. L. Abbott, M. Hsiao, and E. Fox "Extraction of Hierarchical Extended Features in Fingerprint Images," Technical Report, CESCA-2010-001, Bradley Dept. of Electrical and Computer Engineering, Virginia Tech, November 12, 2010.  

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