Next CESCA Seminar is on April 25 (Friday)
CESCA seminars are held on weekly basis during the semester. The speakers are faculty members of CESCA, ECE, and Virginia Tech as well as external speakers, and cover a broad range of topics in electronic system design. It is a great opportunity for CESCA students as well as faculty to broaden one’s knowledge in embedded systems, and attendance of CESCA seminars is strongly recommended.
Please click the date with underline to see the abstract.
|February 7||Dr. Dongyoon Lee, Assistant Professor, Department of Computer Science at Virginia Tech|
|February 14||M. Zubair Shafiq, Ph.D. student at Michigan State University|
|February 21||Sarvesh Prabhu, Ph.D. student, Computer Engineering at Virginia Tech|
|February 28||[CS Distinguished Lecture] Professor Katherine Yelick, U.C. Berkeley|
|March 7||CESCA Coffee+Cake|
|March 21||Dr. Mantu Hudait, Associate Professor, Department of Electrical & Computer Engineering at Virginia Tech|
|March 28||[CS Distinguished Lecture] Dr. Maria Klawe, President at Harvey Mudd College - CANCELED|
|April 4||Dr. Chung-Hsing Hsu, Oak Ridge National Labs|
|April 11||Dr. Dhruv Batra, Assistant Professor, Department of Electrical & Computer Engineering at Virginia Tech|
|April 25||Dr. Rolando Burgos and Dr. Zhiyu Shen, Center for Power Electronics Systems (CPES) at Virginia Tech|
|May 2||Prof. James Yang, Western Michigan University|
|May 8 (Thursday)||Sylvain Guilley, TELECOM ParisTech, Paris, France|
Control system design in power electronics converters
Dr. Rolando Burgos and Dr. Zhiyu Shen, Center for Power Electronics Systems (CPES) at Virginia Tech
2:30pm - 3:30pm on April 25, 2014 (Friday) at Lavery Hall 320
Abstract: Control of power electronics converters varies from analog circuit in simple DC/DC converters to full digital implementations in more complicated systems. At higher power level, the power electronics converters are normally large, expensive, spatially distributed systems. The presentation focuses on a hierarchical control system architecture suitable for high power converters from hundreds of kW to thousands of MW is introduced. The partition of different layers use temporal distribution along with functional distribution as key driving criteria. However, other common restrictions such as spatial distribution and requirement of different technologies usually lead to similar partition result. The signal flow and the behavior of each layer is explained. At last, a few implementation examples of such architecture are given.
Speaker: Dr. Rolando Burgos was born in Concepcion, Chile, where he attended the University of Concepcion, earning his B.S. in Electronics Engineering in 1995 and a Professional Engineering Certificate in Electronics Engineering in 1997, graduating with honors. At the same institution he later earned his M.S. and Ph.D. degrees in Electrical Engineering in 1999 and 2002 respectively.
In 2002 he joined the Center for Power Electronics Systems (CPES) at Virginia Polytechnic Institute and State University (Virginia Tech) in Blacksburg, VA, as Postdoctoral Fellow, where he became Research Scientist in 2003, and Research Assistant Professor in 2005. During this period he was primarily involved in the development and synthesis of high power density power electronics converters and distribution systems, co-advising several Ph.D. and Master students at CPES.
In 2009 he became a Scientist with ABB Corporate Research, in Raleigh, NC, becoming Principal Scientist in 2010. This same year he was appointed Adjunct Associate Professor in the Electrical and Computer Engineering Department at North Carolina State University (NCSU). While at ABB, he was involved in the development of multi-level converter platforms for medium voltage industrial and grid applications.
In 2012 Dr. Burgos returned to The Bradley Department of Electrical and Computer Engineering at Virginia Tech, where he is currently associate professor. His research interests include multi-phase multi-level modular power conversion, grid power electronics applications, high power density power converters, the stability of ac and dc power electronics systems, hierarchical modeling, and control theory and applications. He has co-directed and participated in more than 30 sponsored research projects in this area, and co-authored over 160 peer-reviewed technical publications. He has received three prize paper awards.
Dr. Burgos is a Member of the IEEE and Power Electronics Society, where he currently serves as associate editor of the Transactions on Power Electronics, associate editor of the Power Electronics Letters, and as secretary of the Committee on Modeling, Control and Simulation.
Dr. Zhiyu Shen received the B.S and M.S degrees in electrical engineering from Tsinghua University, Beijing, China, in 2004 and 2007, respectively, and Ph. D. degree from Virginia Tech in 2013. He now works as a research scientist in Center of Power Electronics Systems.
His research interests include three-phase AC system impedance measurement, three-phase AC system small signal stability analysis, high-frequency high-density converter design.
Automated Fault Explanation for Software Regression Testing
Professor Zijiang (James) Yang, Computer Science Department, Western Michigan University
2:30pm - 3:30pm on May 2, 2014 (Friday) at Lavery Hall 320
Abstract: During software development, it is considered good coding practice to conduct regression testing, which determines whether new errors have been introduced into the code with previously working functionality while fixing the existing errors. Some projects even set up automated development systems to re-run all regression tests at specified time intervals and report failures as soon as they appear. However, discovering the errors introduced by a software update is only the first step. The more challenging task is to identify the responsible code changes and explain why they lead to the failures.
In this talk, we propose an automated approach to explain failed regression tests. Given an error-inducing test input, a buggy program, and an earlier correct version, we conduct a symbolic analysis of the relevant execution paths starting from the manifested failure while considering the effect of code changes. The final report includes the root cause as well as the context of the fault propagation, to help improve the programmer’s productivity.
Speaker: Dr. Zijiang James Yang is an associate professor in the Department of Computer Science at Western Michigan University. He holds a Ph.D. degree from the University of Pennsylvania, a M.S. degree from Rice University and a B.S. degree from the University of Science and Technology of China, all in computer science. The primary focus of his research is to develop formal methods and tools that support the modeling, analysis and verification of complex computer systems. Dr. Yang published over fifty conference and journal papers. He received ACM TODAES best paper award in 2008, WMU CEAS Young Researcher Award in 2008, and PADTAD best paper award in 2010.
Mathematical & Formal methods for Secure Design & Evaluation against Non-invasive Attacks
Sylvain Guilley, TELECOM ParisTech, Paris, France
2:30pm - 3:30pm on May 8, 2014 (Thursday) at Lavery Hall 350
Abstract: Embedded systems (smartcards, smartphones, cryptographic modules, etc.) are sensitive to physical attacks, such as side-channel or fault injection analyses. In this talk, I'll present mathematical and formal methods to design and evaluate protections against those attacks. Regarding secure designs, I'll explain that the security of LEMS ("Low Entropy Masking Schemes") such as RSM ("Rotating Sbox Masking") relies on the theory of coding. Then, I'll introduce ODSM ("Orthogonal Direct Sum Masking"), a LEMS that is furthermore capable of detecting faults if the errors belong a code coset. Regarding security evaluation, I'll explain the rationale of mathematically optimal side-channel distinguishers, and introduce a formal framework for the proof of countermeasures to fault attacks (with an example on the bellcore attack).
Speaker: Sylvain Guilley is professor at TELECOM-ParisTech. His group works on the proven security of electronic circuits and embedded systems. His own research interests are trusted computing, cyber-security, secure prototyping in FPGA and ASIC, and formal methods. Sylvain has authored more than one hundred research papers, and about ten patents. He is member of the IACR, the IEEE and senior member of the CryptArchi club. He is alumni from Ecole Polytechnique and TELECOM-ParisTech. In 2010, he has co-founded the Secure-IC company as a spin-off of TELECOM-ParisTech. Since 2012, he organizes the PROOFS workshop, which brings together researchers whose objective is to increase the trust in the security of embedded systems.