Next CESCA Seminar is on March 21 (Friday)
CESCA seminars are held on weekly basis during the semester. The speakers are faculty members of CESCA, ECE, and Virginia Tech as well as external speakers, and cover a broad range of topics in electronic system design. It is a great opportunity for CESCA students as well as faculty to broaden one’s knowledge in embedded systems, and attendance of CESCA seminars is strongly recommended.
Please click the date with underline to see the abstract.
|February 7||Dr. Dongyoon Lee, Assistant Professor, Department of Computer Science at Virginia Tech|
|February 14||M. Zubair Shafiq, Ph.D. student at Michigan State University|
|February 21||Sarvesh Prabhu, Ph.D. student, Computer Engineering at Virginia Tech|
|February 28||[CS Distinguished Lecture] Professor Katherine Yelick, U.C. Berkeley|
|March 7||CESCA Coffee+Cake|
|March 21||Dr. Mantu Hudait, Associate Professor, Department of Electrical & Computer Engineering at Virginia Tech|
|March 28||[CS Distinguished Lecture] Dr. Maria Klawe, President at Harvey Mudd College|
|April 4||Dr. Chung-Hsing Hsu, Oak Ridge National Labs|
|April 11||Dr. Dhruv Batra, Assistant Professor, Department of Electrical & Computer Engineering at Virginia Tech|
|April 25||Prof. Dushan Boroyevich, Prof. Rolando Burgos, CPES students|
|May 2||Prof. James Yang, Western Michigan University|
Extremely High Mobility CMOS Logic
Dr. Mantu K. Hudait, Associate Professor, Dept. of Electrical & Computer Engineering, Virginia Tech
2:30pm - 3:30pm on March 21, 2014 (Friday) at Lavery Hall 320
Abstract: Shrinking feature sizes of CMOS transistor has enabled increase in transistor densities and this rising number of transistors increases the power consumption in ICs. Thus, the computing power is primarily constrained by power consumption and high-speed operation. Low-power consumption would imply lower heat dissipation, prolonged battery life and reduced cooling requirements, which all add up to significant reductions in cost and energy savings. Going forward, transistor scaling will require the introduction of new high mobility channel materials, including III-V and Ge, novel device architectures (quantum well or 3D FinFET) and their heterogeneous integration on highly dense Si CMOS could be a key enabler for lowering power consumption and enhance performance of microprocessor technology. Beyond sub 22 nm technology node, high mobility III-V materials and new device architectures have the potential to provide higher switching speeds and to operate at lower voltage <0.5V than Si FETs. Heterogeneous integration of such high mobility materials with transformative device and circuit architectures configuration have recently emerged a promising option for ultra-high speed and low voltage operation. In this talk, I will present the recent development of the heterogeneous integration of compound semiconductors for n-channel and Ge for p-channel on Si, and mixed As/Sb based staggered gap tunnel transistors research from our group.
Speaker: Dr. Mantu Hudait is an Associate Professor in the Bradley Department of Electrical and Computer Engineering (ECE), Virginia Tech. Prior joining at Virginia Tech, he was a Senior Engineer in the Intel Corporation's Advanced Transistor and Nanotechnology Group. His research at Virginia Tech focuses on next generation nanoscale transistors for low power and high-speed devices as well as multijunction solar cells on low cost silicon substrate. He work was press release in 2007 and 2009 and received two Divisional Recognition Awards from Intel Corporation, 43 US Patents issued, and over 135 technical publications. Dr. Hudait’s teaching focuses on integrating research and industry experience into the curriculum. He is a Senior Member of the IEEE, AVS member and ASEE member.
Advanced Devices & Sustainable Energy Laboratory (ADSEL)
Bradley Department of Electrical and Computer Engineering
Virginia Tech, Blacksburg, VA 24061
E-mail: mantu.hudait [at] vt.edu
TUE, a New Energy-Efficiency Metric Applied at ORNL's Jaguar
Dr. Chung-Hsing Hsu, Oak Ridge National Laboratory
2:30pm - 3:30pm on April 4, 2014 (Friday) at Lavery Hall 320
Abstract: Energy efficiency has become a major concern in high performance computing (HPC). In this talk I will start by mentioning a few ongoing community efforts in energy efficient HPC. Then I will go in depth and discuss one of these efforts. Specifically, I will present a new energy-efficient metric called TUE (Total-power Usage Effectiveness). TUE provides a ratio of total energy,(internal and external support energy uses) and the specific energy used in the HPC. This effort aims to more accurately account for the power distribution and cooling losses while system suppliers are moving power and cooling subsystems into or out of the IT equipment. I will conclude the talk with a case study of measurements at ORNL's Jaguar system.
Speaker: Dr. Chung-Hsing Hsu is an R&D staff member with the Computer Science Group of the Oak Ridge National Laboratory (ORNL). Before joining ORNL in 2009, he was a technical staff member at Los Alamos National Laboratory. Dr. Hsu's expertise is in computer program translation and energy efficient computing. His current research focuses on enhancing power awareness in HPC environments. Hsu has a Ph.D. degree in computer science from Rutgers University.
Hedging Against Uncertainty via Multiple Diverse Predictions
Dr. Dhruv Batra, Assistant Professor, Dept. of Electrical & Computer Engineering, Virginia Tech
2:30pm - 3:30pm on April 11, 2014 (Friday) at Lavery Hall 320
Abstract: Perception problems are hard. Whether it is object detection, pose estimation, or scene understanding, vision systems must deal with tremendous amounts of noise and ambiguity.
Unfortunately, idealized probabilistic models for dealing with this uncertainty are typically computationally intractable. This leads to a major formal divide -- we either a) make performance-limiting assumptions and end up with restricted probabilistic models (e.g. "attractive" pairwise MRFs) that don't work too well; or b) abandon the probabilistic framework in favor of rich feed-forward "pipelines" (pixels --> regions --> labels) that mismanage uncertainty.
In this talk, I will give a high-level sampling of some projects in my lab. As a specific example, we have developed a two-stage image segmentation model where the first stage is a tractable probabilistic model that outputs not just a single-best solution, rather a /diverse/ set of plausible solutions or guesses. The second stage is a discriminative re-ranker that is free to exploit arbitrarily complex features, and attempts to pick out the best solution from this set. This hybrid model has recently achieved state-of-art performance on Pascal VOC 2012 segmentation dataset.
Joint work with Students: Abner Guzman-Rivera (UIUC), Ankit Laddha (VT), Adarsh Prasad (VT/UT-Austin), Qing Sun (VT), Payman Yadollahpour (TTIC); Collaborators: Chris Dyer (CMU), Kevin Gimpel (TTIC), Stefanie Jegelka (UC Berekely), Pushmeet Kohli (MSRC), Greg Shakhnarovich (TTIC), Danny Tarlow (MSRC).
Speaker: (cited from: https://filebox.ece.vt.edu/~dbatra/files/bio.txt) Dhruv Batra is an Assistant Professor at the Bradley Department of Electrical and Computer Engineering at Virginia Tech, where he leads the VT Machine Learning & Perception group. He is a member of the Virginia Center for Autonomous Systems (VaCAS) and the VT Discovery Analytic Center (DAC).
Prior to joining VT, he was a Research Assistant Professor at Toyota Technological Institute at Chicago (TTIC), a philanthropically endowed academic computer science institute located in the campus of University of Chicago. He received his M.S. and Ph.D. degrees from Carnegie Mellon University in 2007 and 2010 respectively, advised by Tsuhan Chen. In past, he has held visiting positions at the Machine Learning Department at CMU, CSAIL MIT, Microsoft Research Cambridge and Cornell University.
His research interests lie at the intersection of machine learning, computer vision and AI, with a focus on developing scalable algorithms for learning and inference in probabilistic models for holistic scene understanding. He has also worked on other topics such as interactive co-segmentation of large image collections, human body pose estimation, action recognition, depth estimation and distributed optimization for inference and learning in probabilistic graphical models.
He was a recipient of the Carnegie Mellon Dean's Fellowship in 2007, the Google Faculty Research Award in 2013, and the Virginia Tech Teacher of the Week in 2013. His research is supported by NSF, Google, Amazon, and Microsoft.
Automated Fault Explanation for Software Regression Testing
Professor Zijiang (James) Yang, from the CS Department, Western Michigan University
2:30pm - 3:30pm on May 2, 2014 (Friday) at Lavery Hall 320
Abstract: During software development, it is considered good coding practice to conduct regression testing, which determines whether new errors have been introduced into the code with previously working functionality while fixing the existing errors. Some projects even set up automated development systems to re-run all regression tests at specified time intervals and report failures as soon as they appear. However, discovering the errors introduced by a software update is only the first step. The more challenging task is to identify the responsible code changes and explain why they lead to the failures.
In this talk, we propose an automated approach to explain failed regression tests. Given an error-inducing test input, a buggy program, and an earlier correct version, we conduct a symbolic analysis of the relevant execution paths starting from the manifested failure while considering the effect of code changes. The final report includes the root cause as well as the context of the fault propagation, to help improve the programmer’s productivity.
Speaker: Dr. Zijiang James Yang is an associate professor in the Department of Computer Science at Western Michigan University. He holds a Ph.D. degree from the University of Pennsylvania, a M.S. degree from Rice University and a B.S. degree from the University of Science and Technology of China, all in computer science. The primary focus of his research is to develop formal methods and tools that support the modeling, analysis and verification of complex computer systems. Dr. Yang published over fifty conference and journal papers. He received ACM TODAES best paper award in 2008, WMU CEAS Young Researcher Award in 2008, and PADTAD best paper award in 2010.