High-Speed, Low-Power Circuit Design Publications
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- J-S. Lee, and D.S. Ha, “High Speed 1-bit Bypass Adder Design for Low Precision Additions,” to appear in International Symposium on Circuits and Systems, May 2007.
- N.J. August and D.S. Ha, “Low Power Design of DCT and IDCT for Low Bit Rate Video Codecs,” IEEE Transactions on Multimedia, Vol. 6, No. 3, pp. 414-422, June 2004.
- V. Srinivasan, D.S. Ha, and J.B. Sulistyo, "Gigahertz-Range MCML Multiplier Architectures," International Symposium on Circuits and Systems, Volume II, pp. 785-788, May 2004.
- J.B. Sulistyo and D.S. Ha, "5 GHz Pipelined Multiplier and Mac in 0.18 um Complementary Static CMOS," International Symposium on Circuits and Systems, pp. 117-120, May 2003.
- J.B. Sulistyo and D.S. Ha, "HyPipe: A New Approach for High Speed Circuit Design," IEEE International ASIC/SOC Conference, pp. 203-207, September 2002.
- C. Aust and D.S. Ha, "A Low-Power Variable Resolution Analog-to-Digital Converter," IEEE International ASIC/SOC Conference, pp. 460-463, September 2001.
- N. August and D.S. Ha, " On the Low-Power Design of DCT and IDCT for Low Bit Rate Video Codecs," IEEE International ASIC/SOC Conference, pp. 203-207, September 2001.
- S. Richmond and D.S. Ha, " A Low-Power Motion Estimation Block for Low Bit-Rate Wireless Video," International Symposium on Low Power Electronics and Design, pp. 60-63, August 2001.
- M. Jagasivamani and D.S. Ha, "Development of a Low-Power SRAM Compiler," International Conference on Circuits and Systems, Volume 4, pp. 498-501, May 2001.
