• Overview
• Projects
• Publications
  • By Area
  • By Faculty
  • By Year
• Reports
• Sponsors
• Open Position

Testing and Various Topics Publications

This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

• J-S. Lee, and D.S. Ha, "FleXilicon: a Reconfigurable Architecture for Multimedia and Wireless Communications," International Symposium on Circuits and Systems, pp. 4375-4378, May 2006.


• R.C. Palat, J. Kim, J.S. Lee, D.S. Ha, C. Patterson, and J.H. Reed, “Reconfigurable Modem Architecture for CDMA Based 3G Handsets,” 2005 Software Defined Radio Technical Conference and Product Exposition, Session 1.4-01 (7 pages), November, 2005.


• W.C. Chung, and D.S. Ha, “A New Approach for Massive Parallel Scan,” International Test Conference, Paper 21.3, pp. 1-10, November 2005.


• S. Yardi, K. Channakeshava, M.S Hsiao, T. Martin, D.S. Ha, “A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management,” International Conference on Computer Design, pp. 119-126, October 2005.


• W.C. Chung, D.S. Ha, and H.-J. Lee, “Dual Use of Power Lines for Data Communications in System-On-Chips Environments,” International Symposium on Circuits and Systems, pp. 3355–3358, May 2005.


• J. Kim, D.S. Ha, and J.H. Reed, “A New Reconfigurable Modem Architecture for 3G Multi-Standard Wireless Communication Systems,” International Symposium on Circuits and Systems, pp. 1051–1054, May 2005.


• D. Nash, T.L. Martin, D.S. Ha, and M.S. Hsiao, “Towards an Intrusion Detection System for Battery Exhaustion Attacks on Mobile Computing Devices,” Second IEEE International Workshop on Pervasive Computing and Communication Security, pp. 141-145, March 2005.


• S.M. Yardi, M.S. Hsiao, T.L. Martin, and D.S. Ha “Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing,” Proceedings on Design Automation and Test in Europe (DATE), pp. 340-345, March, 2005.


• T. Martin, M. Hsiao, D.S. Ha, and J. Krishnaswami, "Denial-of-Service Attacks on Battery-Powered Mobile Computers," Second IEEE International Conference on Pervasive Computing and Communications, pp. 309-318, March 2004.


• J.B. Sulistyo and D.S. Ha, "New Characterization Method for Delay and Power Dissipation of Standard Library Cells," Journal of VLSI Design, Vol.15, No. 3, pp. 667-678, November 2002.


• M. Ishida, D.S. Ha, T. Yamaguchi, Y. Hashimoto, and T. Ohmi, "I_DDT Testing: An Efficient Method for Detecting Delay Faults and Open Defects," IEEE International Workshop on Defect Based Testing, pp. 23-28, April 2001.


• S. Yoo, K. Choi, and D.S. Ha, "Performance Improvement of Geographically Distributed Cosimulation by Hierarchically Grouped Messages," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, pp. 492-502, October 2000.


• H.B. Kim and D.S. Ha, "Design and Synthesis of Built-In Self-Testable Two-Dimensional Discrete Cosine Transform Circuits," IEEE International ASIC/SOC Conference, September 2000.


• H.B. Kim and D.S. Ha, "A High-Level BIST Synthesis Method Based on a Region-wise Heuristic for an Integer Linear Programming," Proceedings of International Test Conference, pp. 903-912, September 1999.


• H.B. Kim, D.S. Ha, and T. Takahashi, "On ILP Formulations for Built-In Self-Testable Data Path Synthesis," Proceedings of 36th Design Automation Conference, pp. 742-747, June 1999.


• H.B. Kim, T. Takahashi, and D.S. Ha, "Test Session Oriented Built-In Self-Testable Data Path Synthesis," Proceedings of International Test Conference, pp. 154-163, October 1998.


• M. Ishida, D.S. Ha, and T. Yamaguchi, "COMPACT: A Hybrid Method for Compressing Test Data," Proceedings of VLSI Test Symposium, pp. 62-69, April 1998.


• H.K. Lee and D.S. Ha, " HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, pp. 1048-1058, September 1996.